用于高速视频信号数字化仪的10位200MS/s流水线A/D转换器

T. Nezuka, K. Misawa, J. Azami, Y. Majima, J. Okamura
{"title":"用于高速视频信号数字化仪的10位200MS/s流水线A/D转换器","authors":"T. Nezuka, K. Misawa, J. Azami, Y. Majima, J. Okamura","doi":"10.1109/ASSCC.2006.357844","DOIUrl":null,"url":null,"abstract":"A 10-bit 200MS/s A/D converter (ADC) for highspeed video signal digitizer is presented. The ADC has a 14- bit pipeline ADC core for digital programmable gain control and a reference voltage buffer optimized for high-speed A/D conversion. The ADC is fabricated in a 0.18-mum multiple Vth CMOS process. The area of ADC core is 1.15 mmtimes0.69 mm, and power consumption is 128 mW@200 MS/s. The measured INL and DNL are 1.05 LSB and 0.55 LSB respectively. The measured SNR and SFDR are 54.8 dB and 63.2 dB respectively.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"27","resultStr":"{\"title\":\"A 10-bit 200MS/s Pipeline A/D Converter for High-Speed Video Signal Digitizer\",\"authors\":\"T. Nezuka, K. Misawa, J. Azami, Y. Majima, J. Okamura\",\"doi\":\"10.1109/ASSCC.2006.357844\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 10-bit 200MS/s A/D converter (ADC) for highspeed video signal digitizer is presented. The ADC has a 14- bit pipeline ADC core for digital programmable gain control and a reference voltage buffer optimized for high-speed A/D conversion. The ADC is fabricated in a 0.18-mum multiple Vth CMOS process. The area of ADC core is 1.15 mmtimes0.69 mm, and power consumption is 128 mW@200 MS/s. The measured INL and DNL are 1.05 LSB and 0.55 LSB respectively. The measured SNR and SFDR are 54.8 dB and 63.2 dB respectively.\",\"PeriodicalId\":142478,\"journal\":{\"name\":\"2006 IEEE Asian Solid-State Circuits Conference\",\"volume\":\"55 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"27\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE Asian Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2006.357844\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2006.357844","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 27

摘要

介绍了一种用于高速视频信号数字化仪的10位200MS/s A/D转换器(ADC)。该ADC具有用于数字可编程增益控制的14位流水线ADC核心和用于高速a /D转换优化的参考电压缓冲器。该ADC采用0.18 μ m多Vth CMOS工艺制造。ADC核心面积为1.15 mmtimes0.69 mm,功耗为128 mW@200 MS/s。测得INL和DNL分别为1.05 LSB和0.55 LSB。测量的信噪比和SFDR分别为54.8 dB和63.2 dB。
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A 10-bit 200MS/s Pipeline A/D Converter for High-Speed Video Signal Digitizer
A 10-bit 200MS/s A/D converter (ADC) for highspeed video signal digitizer is presented. The ADC has a 14- bit pipeline ADC core for digital programmable gain control and a reference voltage buffer optimized for high-speed A/D conversion. The ADC is fabricated in a 0.18-mum multiple Vth CMOS process. The area of ADC core is 1.15 mmtimes0.69 mm, and power consumption is 128 mW@200 MS/s. The measured INL and DNL are 1.05 LSB and 0.55 LSB respectively. The measured SNR and SFDR are 54.8 dB and 63.2 dB respectively.
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