{"title":"基于冗余INL直方图估计的管道adc非线性校准","authors":"A. Ginés, G. Léger, E. Peralías","doi":"10.1109/newcas49341.2020.9159800","DOIUrl":null,"url":null,"abstract":"This paper presents a digital non-linear calibration technique for Pipeline ADCs using a novel Look-up Table (LUT) approach. Due to redundancy, the signal paths (and hence, the errors in Pipeline ADCs) are not unique for a given input level. This effect limits the performance of conventional LUT -based calibration methods using the output code of the ADC as single address in the error code LUT memory. To overcome this drawback, this work uses an estimation of true redundant INL (Integral Non-Linearity), based on the standardized histogram method. The technique resolves the presence of multiple error codes for a single input level incorporating the most significant redundant subcodes in the memory address. The advantages of the method are shown by realistic behavioral simulations and by a 0.8Vpp 11-bit 60Msps Pipeline ADC silicon demonstrator in a 130nm CMOS process.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Non-Linear Calibration of Pipeline ADCs using a Histogram-Based Estimation of the Redundant INL\",\"authors\":\"A. Ginés, G. Léger, E. Peralías\",\"doi\":\"10.1109/newcas49341.2020.9159800\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a digital non-linear calibration technique for Pipeline ADCs using a novel Look-up Table (LUT) approach. Due to redundancy, the signal paths (and hence, the errors in Pipeline ADCs) are not unique for a given input level. This effect limits the performance of conventional LUT -based calibration methods using the output code of the ADC as single address in the error code LUT memory. To overcome this drawback, this work uses an estimation of true redundant INL (Integral Non-Linearity), based on the standardized histogram method. The technique resolves the presence of multiple error codes for a single input level incorporating the most significant redundant subcodes in the memory address. The advantages of the method are shown by realistic behavioral simulations and by a 0.8Vpp 11-bit 60Msps Pipeline ADC silicon demonstrator in a 130nm CMOS process.\",\"PeriodicalId\":135163,\"journal\":{\"name\":\"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/newcas49341.2020.9159800\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/newcas49341.2020.9159800","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Non-Linear Calibration of Pipeline ADCs using a Histogram-Based Estimation of the Redundant INL
This paper presents a digital non-linear calibration technique for Pipeline ADCs using a novel Look-up Table (LUT) approach. Due to redundancy, the signal paths (and hence, the errors in Pipeline ADCs) are not unique for a given input level. This effect limits the performance of conventional LUT -based calibration methods using the output code of the ADC as single address in the error code LUT memory. To overcome this drawback, this work uses an estimation of true redundant INL (Integral Non-Linearity), based on the standardized histogram method. The technique resolves the presence of multiple error codes for a single input level incorporating the most significant redundant subcodes in the memory address. The advantages of the method are shown by realistic behavioral simulations and by a 0.8Vpp 11-bit 60Msps Pipeline ADC silicon demonstrator in a 130nm CMOS process.