Planarization of topography with spin-on carbon hard mask

Spin-on-carbon hard mask (SOC HM) has been used in semiconductor manufacturing since 45nm node as an alternative carbon hard mask process to chemical vapor deposition (CVD). As advancement of semiconductor to 2X nm nodes and beyond, multiple patterning technology is used and planarization of topography become more important and challenging ever before. In order to develop next generation SOC, one of focuses is planarization of topography. SOC with different concepts for improved planarization and the influence of thermal flow temperature, crosslink, film shrinkage, baking conditions on planarization and filling performance are described in this paper.