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SEM based overlay measurement between resist and buried patterns 基于扫描电镜的电阻和埋地模式之间的覆盖测量
Pub Date : 2016-04-27 DOI: 10.1117/12.2221910
O. Inoue, Y. Okagawa, K. Hasumi, Chuanyu Shao, P. Leray, G. Lorusso, B. Baudemprez
With the continuous shrink in pattern size and increased density, overlay control has become one of the most critical issues in semiconductor manufacturing. Recently, SEM based overlay of AEI (After Etch Inspection) wafer has been used for reference and optimization of optical overlay (both Image Based Overlay (IBO) and Diffraction Based Overlay (DBO)). Overlay measurement at AEI stage contributes monitor and forecast the yield after formation by etch and calibrate optical measurement tools. however those overlay value seems difficult directly for feedback to a scanner. Therefore, there is a clear need to have SEM based overlay measurements of ADI (After Develop Inspection) wafers in order to serve as reference for optical overlay and make necessary corrections before wafers go to etch. Furthermore, to make the corrections as accurate as possible, actual device like feature dimensions need to be measured post ADI. This device size measurement is very unique feature of CDSEM , which can be measured with smaller area. This is currently possible only with the CD-SEM. This device size measurement is very unique feature of CD-SEM , which can be measured with smaller area. In this study, we assess SEM based overlay measurement of ADI and AEI wafer by using a sample from an N10 process flow. First, we demonstrate SEM based overlay performance at AEI by using dual damascene process for Via 0 (V0) and metal 1 (M1) layer. We also discuss the overlay measurements between litho-etch-litho stages of a triple patterned M1 layer and double pattern V0. Second, to illustrate the complexities in image acquisition and measurement we will measure overlay between M1B resist and buried M1A-Hard mask trench. Finally, we will show how high accelerating voltage can detect buried pattern information by BSE (Back Scattering Electron). In this paper we discuss the merits of this method versus standard optical metrology based corrections.
随着图案尺寸的不断缩小和密度的不断增加,覆盖层控制已成为半导体制造中最关键的问题之一。近年来,基于扫描电镜(SEM)的AEI (After Etch Inspection)晶圆覆盖被用于参考和优化光学覆盖(基于图像的覆盖(IBO)和基于衍射的覆盖(DBO))。AEI阶段的覆盖测量有助于通过蚀刻和校准光学测量工具监测和预测成品率。然而,这些叠加值似乎很难直接反馈给扫描仪。因此,显然需要对ADI(开发后检查)晶圆进行基于SEM的覆盖测量,以便作为光学覆盖的参考,并在晶圆进入蚀刻之前进行必要的校正。此外,为了使校正尽可能准确,需要在ADI后测量实际设备的特征尺寸。这种器件尺寸测量是CDSEM非常独特的特点,可以用更小的面积进行测量。目前只有使用CD-SEM才能做到这一点。这种器件尺寸测量是CD-SEM非常独特的特点,可以用更小的面积进行测量。在本研究中,我们通过使用N10工艺流程中的样品来评估基于SEM的ADI和AEI晶圆的覆盖测量。首先,我们通过对Via 0 (V0)和金属1 (M1)层使用双大马士革工艺,证明了基于SEM的AEI覆盖性能。我们还讨论了三图案M1层和双图案V0层的光刻-刻蚀-光刻阶段之间的覆盖测量。其次,为了说明图像采集和测量的复杂性,我们将测量M1B抗蚀剂和埋置M1A-Hard掩膜沟槽之间的覆盖层。最后,我们将展示高加速电压如何通过反向散射电子(BSE)检测隐藏图案信息。本文讨论了该方法相对于基于标准光学计量校正的优点。
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引用次数: 10
Contrast optimization for 0.33NA EUV lithography 0.33NA EUV光刻对比度优化
Pub Date : 2016-04-26 DOI: 10.1117/12.2220036
J. Finders, S. Wuister, T. Last, G. Rispens, Eleni Psari, J. Lubkoll, E. van Setten, F. Wittebrood
0.33 NA EUV lithography is expected to be introduced into High Volume Manufacturing at k1 values of approximately 0.4...0.5. This is significantly larger than state of the art immersion lithography which can operate at k1 of 0.3. We investigated the impact of contrast enhancement on the imaging properties of Contact Holes and Lines and Spaces. Contrast was adjusted by changing the illumination properties pupil fill ratio and center incidence angle. We found a strong improvement of the local Critical Dimension control: line width variation for Lines and Spaces and hole to hole CD variations for arrays of contact holes. For all features we found a similar dependency on contrast. As the local Critical Dimension variations contribute significant to Edge Placement Error budgets, we foresee the implementation of contrast enhancements already at moderate k1 values around 0.4.
预计在k1值约为0.4…0.5的情况下,0.33 NA EUV光刻技术将被引入大批量生产。这比目前最先进的浸入式光刻技术要大得多,后者的k1为0.3。我们研究了对比度增强对接触孔、线和空间成像特性的影响。通过改变照明特性、瞳孔填充比和中心入射角来调整对比度。我们发现了局部临界尺寸控制的强大改进:线和空间的线宽变化以及接触孔阵列的孔间CD变化。对于所有的特性,我们都发现了类似的对对比度的依赖。由于局部关键维度的变化对边缘放置误差预算贡献很大,我们预计对比度增强的实现已经在0.4左右的适度k1值。
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引用次数: 27
Improving reticle defect disposition via fully automated lithography simulation 通过全自动光刻模拟改进光刻线缺陷处理
Pub Date : 2016-04-21 DOI: 10.1117/12.2230847
R. Mann, E. Goodman, K. Lao, Steven Ha, A. Vacca, P. Fiekowsky, Dan Fiekowsky
Most advanced wafer fabs have embraced complex pattern decoration, which creates numerous challenges during in-fab reticle qualification. These optical proximity correction (OPC) techniques create assist features that tend to be very close in size and shape to the main patterns as seen in Figure 1. A small defect on an assist feature will most likely have little or no impact on the fidelity of the wafer image, whereas the same defect on a main feature could significantly decrease device functionality. In order to properly disposition these defects, reticle inspection technicians need an efficient method that automatically separates main from assist features and predicts the resulting defect impact on the wafer image. Analysis System (ADAS) defect simulation system[1]. Up until now, using ADAS simulation was limited to engineers due to the complexity of the settings that need to be manually entered in order to create an accurate result. A single error in entering one of these values can cause erroneous results, therefore full automation is necessary. In this study, we propose a new method where all needed simulation parameters are automatically loaded into ADAS. This is accomplished in two parts. First we have created a scanner parameter database that is automatically identified from mask product and level names. Second, we automatically determine the appropriate simulation printability threshold by using a new reference image (provided by the inspection tool) that contains a known measured value of the reticle critical dimension (CD). This new method automatically loads the correct scanner conditions, sets the appropriate simulation threshold, and automatically measures the percentage of CD change caused by the defect. This streamlines qualification and reduces the number of reticles being put on hold, waiting for engineer review. We also present data showing the consistency and reliability of the new method, along with the impact on the efficiency of in-fab reticle qualification.
大多数先进的晶圆厂都采用了复杂的图案装饰,这给厂内网线的鉴定带来了许多挑战。这些光学接近校正(OPC)技术创建的辅助特征往往在尺寸和形状上与图1所示的主要图案非常接近。辅助功能上的小缺陷很可能对晶圆图像的保真度几乎没有影响,而主要功能上的相同缺陷可能会显著降低设备的功能。为了正确地处理这些缺陷,光线检测技术人员需要一种有效的方法来自动分离主要特征和辅助特征,并预测由此产生的缺陷对晶圆图像的影响。分析系统(ADAS)缺陷仿真系统[1]。到目前为止,由于需要手动输入以创建准确结果的设置的复杂性,使用ADAS仿真仅限于工程师。输入这些值中的一个错误可能导致错误的结果,因此需要完全自动化。在本研究中,我们提出了一种新的方法,将所有需要的仿真参数自动加载到ADAS中。这分两部分完成。首先,我们创建了一个扫描器参数数据库,该数据库可以从掩膜产品和级别名称中自动识别。其次,我们通过使用包含已知的十字线临界尺寸(CD)测量值的新参考图像(由检测工具提供)自动确定适当的模拟可打印性阈值。这种新方法自动加载正确的扫描条件,设置适当的模拟阈值,并自动测量由缺陷引起的CD变化的百分比。这简化了资格认证,减少了搁置等待工程师审查的线路数量。我们还提供了数据,显示了新方法的一致性和可靠性,以及对厂内网线鉴定效率的影响。
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引用次数: 1
Spectroscopic imaging of buried layers in 2+1D via tabletop ptychography with high-harmonic EUV illumination 高谐波EUV照射下桌面平面摄影的2+1D埋层光谱成像
Pub Date : 2016-04-21 DOI: 10.1117/12.2220368
D. Gardner, Christina L. Porter, E. Shanblatt, G. Mancini, Robert M. Karl, M. Tanksalvala, C. Bevis, H. Kapteyn, M. Murnane, D. Adams
We use EUV coherent microscopy to obtain high-resolution images of buried interfaces, with chemical specificity, in 2+1 dimensions. We perform reflection mode, ptychographic, coherent diffractive imaging with tabletop EUV light, at 29nm, produced by high harmonic generation. Our damascene-style samples consist of copper structures inlaid in SiO2, polished nearly flat with chemical mechanical polishing. We obtain images of both an unaltered damascene as well as one buried below a 100nm thick layer of evaporated aluminum. The aluminum is opaque to visible light and thick enough that neither optical microscopy, SEM, nor AFM can access the buried interface. EUV microscopy is able to image the buried structures, non-destructively, in conditions where other techniques cannot.
我们使用EUV相干显微镜在2+1维度上获得具有化学特异性的埋藏界面的高分辨率图像。我们使用桌面EUV光进行反射模式、平面成像、相干衍射成像,波长为29nm,由高谐波产生。我们的大马士革风格样品由镶嵌在SiO2中的铜结构组成,用化学机械抛光抛光得几乎平整。我们获得了未改变的大马士革的图像,以及埋在100纳米厚的蒸发铝层下面的图像。铝对可见光是不透明的,而且足够厚,光学显微镜、扫描电镜和原子力显微镜都无法进入隐藏的界面。在其他技术无法做到的条件下,EUV显微镜能够对埋藏结构进行非破坏性成像。
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引用次数: 1
Analysis of wafer heating in 14nm DUV layers 14nm DUV层晶圆加热分析
Pub Date : 2016-04-21 DOI: 10.1117/12.2218724
Lokesh Subramany, W. Chung, Pavan Samudrala, Haiyong Gao, N. Aung, Juan-Manuel Gomez, B. Minghetti, Shawn Lee
To further shrink the contact and trench dimensions, Negative Tone Development (NTD) has become the de facto process at these layers. The NTD process uses a positive tone resist and an organic solvent-based negative tone developer which leads to improved image contrast, larger process window and smaller Mask Error Enhancement Factor (MEEF)[1]. The NTD masks have high transmission values leading to lens heating and as observed here wafer heating as well. Both lens and wafer heating will contribute to overlay error, however the effects of lens heating can be mitigated by applying lens heating corrections while no such corrections exist for wafer heating yet. Although the magnitude of overlay error due to wafer heating is low relative to lens heating; ever tightening overlay requirements imply that the distortions due to wafer heating will quickly become a significant part of the overlay budget. In this work the effects, analysis and observations of wafer heating on contact and metal layers of the 14nm node are presented. On product wafers it manifests as a difference in the scan up and scan down signatures between layers. An experiment to further understand wafer heating is performed with a test reticle that is used to monitor scanner performance.
为了进一步缩小接触和沟槽尺寸,负色调发展(NTD)已成为这些层的事实上的过程。NTD工艺使用正色调抗蚀剂和有机溶剂基负色调显影剂,从而提高了图像对比度,增大了工艺窗口,减小了掩模误差增强因子(MEEF)[1]。NTD掩模具有高透射值,导致透镜加热,正如这里观察到的,晶圆加热也是如此。透镜和晶圆加热都会导致叠加误差,但是透镜加热的影响可以通过透镜加热校正来减轻,而晶圆加热还没有这样的校正。虽然由于晶圆加热的叠加误差的大小相对于透镜加热是低的;越来越严格的覆盖要求意味着由于晶圆加热造成的扭曲将很快成为覆盖预算的重要组成部分。本文介绍了晶圆加热对14nm节点接触层和金属层的影响、分析和观察。在产品晶圆上,它表现为层之间向上扫描和向下扫描特征的差异。一个实验,以进一步了解晶圆加热进行了测试网线,用于监测扫描仪的性能。
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引用次数: 10
Study of design-based e-beam defect inspection for hotspot detection and process window characterization on 10nm logic device 基于设计的电子束缺陷检测在10nm逻辑器件上的热点检测和工艺窗口表征研究
Pub Date : 2016-04-21 DOI: 10.1117/12.2218971
P. Leray, S. Halder, P. Di Lorenzo, Fei Wang, Pengcheng Zhang, Wei Fang, Kevin Liu, J. Jau
With the continuous shrink of design rules from 14nm to 10nm to 7nm, conserving process windows in a high volume manufacturing environment is becoming more and more difficult. Masks, scanners, and etch processes have to meet very tight specifications in order to keep defect, CD, as well as overlay within the margins of the process window. In this work, we study a design-based e-beam defect inspection technology for wafer level process window characterization and intra-field defect variability on 10nm logic devices. Due to high resolution, e-beam technology is the natural choice for review and/or detection of subtle pattern deviations, aka defects. The capability of integrating design information (GDS file) with defect detection, dimension measurement of critical structure, and defect classification provides added values for engineers to identify yield limiting systematic defects and to provide feedback to design.
随着设计规则从14nm到10nm再到7nm的不断缩小,在大批量制造环境下节约工艺窗口变得越来越困难。掩模、扫描仪和蚀刻工艺必须满足非常严格的规范,以保持缺陷、CD以及覆盖在工艺窗口的边缘内。在这项工作中,我们研究了一种基于设计的电子束缺陷检测技术,用于10nm逻辑器件的晶圆级工艺窗口表征和场内缺陷可变性。由于高分辨率,电子束技术是审查和/或检测细微的模式偏差,又名缺陷的自然选择。将设计信息(GDS文件)与缺陷检测、关键结构尺寸测量和缺陷分类相结合的能力为工程师识别限制产量的系统缺陷并为设计提供反馈提供了附加价值。
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引用次数: 4
Characterization of cross-sectional profile of resist L/S and hole pattern using CD-SAXS 利用CD-SAXS表征抗蚀剂的L/S截面和孔型
Pub Date : 2016-04-21 DOI: 10.1117/12.2218983
Yoshiyasu Ito, A. Higuchi, K. Omote
Critical dimension small-angle x-ray scattering (CD-SAXS) with a grazing-incidence geometry, which was recently developed by the authors, has been successfully applied to the cross-sectional profile measurements of different types of L/S- and hole-type patterns on photoresist surfaces. We have calculated diffraction intensities from the nanostructures based on a distorted wave Born approximation method to take the refraction and the reflection at the interfaces between layers into account, and the average cross-sectional profiles have been analyzed by a model-based least-square method. From the precise analyses, slight cross-sectional profile differences of a few nanometers scale generated by using different material and exposure conditions have been identified. The obtained cross-sectional profiles showed good agreements with the results obtained by cross-sectional scanning electron microscopy (SEM). These results demonstrate the applicability of the CD-SAXS to the nanoscale structural metrology. It is expected that the CD-SAXS is also applicable to even smaller scale structures, e.g., those of EUV, NIL, or DSA, as the x-ray wavelength is well shorter than the critical lengths of these structures.
基于掠入射几何的临界尺寸小角度x射线散射(CD-SAXS)已成功应用于光刻胶表面不同类型L/S和孔型图案的截面轮廓测量。考虑层间界面处的折射和反射,采用畸变波玻恩近似法计算了纳米结构的衍射强度,并采用基于模型的最小二乘法对平均截面进行了分析。通过精确分析,确定了不同材料和不同暴露条件下产生的几纳米尺度的微小截面轮廓差异。所得的横截面与扫描电镜(SEM)结果吻合较好。这些结果证明了CD-SAXS在纳米尺度结构测量中的适用性。预计CD-SAXS也适用于更小的尺度结构,例如EUV, NIL或DSA,因为x射线波长远短于这些结构的临界长度。
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引用次数: 8
Modeling ellipsometric measurement of novel 3D structures with RCWA and FEM simulations 基于RCWA和FEM的新型三维结构椭偏测量建模
Pub Date : 2016-04-21 DOI: 10.1117/12.2219270
Samuel O’Mullane, Nick Keller, A. Diebold
Using rigorous coupled wave analysis (RCWA) and finite element method (FEM) simulations together, many interesting ellipsometric measurements can be investigated. This work specifically focuses on simulating copper grating structures that are plasmonically active. Looking at near-field images and Mueller matrix spectra, understanding of physical phenomena is possible. A general strategy for combatting convergence difficulties in RCWA simulations is proposed and applied. The example used is a copper cross-grating structure with known slow convergence.
将严格耦合波分析(RCWA)和有限元法(FEM)模拟结合起来,可以研究许多有趣的椭偏测量。这项工作特别侧重于模拟具有等离子体活性的铜光栅结构。观察近场图像和穆勒矩阵光谱,了解物理现象是可能的。提出并应用了一种解决RCWA模拟中收敛困难的一般策略。所使用的例子是一个铜交叉光栅结构,具有已知的慢收敛。
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引用次数: 3
Detection of metallic buried void by effective density contrast mode 有效密度对比法探测金属埋藏空洞
Pub Date : 2016-04-21 DOI: 10.1117/12.2219186
M. Lei, Kevin Wu, Qing Tian, Kewen Gao, Yaqiong Chen, Haokun Hu, Derek Tomlinson, C. Lei, Yan Zhao
For sub-2Xnm technology nodes, metallic buried voids in metal contacts have become critical yield and reliability issue for high volume semiconductor device manufacturing. Especially as the scaling continues, void-free metal filling becomes more challenging for advanced technology development, which poses great need for effective in-line detection methodology. In this paper we demonstrate comprehensive study of a special buried metallic void detection mode by backscatter electron (BSE) signals based on effective density contrast (EDC), especially for the case of partial conduction while the conventional voltage contrast (VC) mode has no detection due to minimum detectable resistance difference requirement. Successful application of EDC mode in buried metallic void detection by in-line electron beam inspection (EBI) is presented on various metal contact chemical mechanical planarization (CMP) layers, together with Monte Carlo simulations and other characterization methodology which show consistent correlation with experimental observations. Thus an extrapolation based on simulation result is illustrated to predict the detection capability of EDC mode in buried metallic void detection for the popular metal contact material systems including tungsten and copper. Despite of the detection limitation as well as potential damage by the charged particle exposure, EDC mode is demonstrated as a very effective detection methodology for buried metallic void in advanced technology development.
对于亚2xnm技术节点,金属触点中的金属埋藏空洞已成为大批量半导体器件制造的关键良率和可靠性问题。特别是随着结垢的不断进行,无空隙金属充填对先进技术的发展变得更加具有挑战性,这就迫切需要有效的在线检测方法。本文综合研究了一种基于有效密度对比(EDC)的背散射电子(BSE)信号的特殊埋藏金属空洞检测模式,特别是在部分导通的情况下,而传统的电压对比(VC)模式由于可检测电阻差要求最小而无法检测。介绍了EDC模式在各种金属接触化学机械平面化(CMP)层的在线电子束检测(EBI)中的成功应用,以及蒙特卡罗模拟和其他表征方法,这些方法与实验观察结果具有一致的相关性。基于仿真结果的外推,预测了EDC模式对钨、铜等常用金属接触材料体系的埋地金属空洞探测能力。尽管EDC模式存在检测局限性和带电粒子暴露的潜在损伤,但随着技术的发展,EDC模式已被证明是一种非常有效的埋藏金属空洞检测方法。
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引用次数: 4
Lensless hyperspectral spectromicroscopy with a tabletop extreme-ultraviolet source 无透镜高光谱显微镜与桌面极紫外源
Pub Date : 2016-04-21 DOI: 10.1117/12.2220711
D. Gardner, Bosheng Zhang, M. Seaberg, E. Shanblatt, Christina L. Porter, Robert M. Karl, C. Mancuso, H. Kapteyn, M. Murnane, D. Adams
We demonstrate hyperspectral coherent imaging in the EUV spectral region for the first time, without the need for hardware-based wavelength separation. This new scheme of spectromicroscopy is the most efficient use of EUV photons for imaging because there is no energy loss from mirrors or monochromatizing optics. An EUV spectral comb from a tabletop high-harmonic source, centered at a wavelength of 30nm, illuminates the sample and the scattered light is collected on a pixel-array detector. Using a lensless imaging technique known as ptychographical information multiplexing, we simultaneously retrieve images of the spectral response of the sample at each individual harmonic. We show that the retrieved spectral amplitude and phase agrees with theoretical predictions. This work demonstrates the power of coherent EUV beams for rapid material identification with nanometer-scale resolution.
我们首次展示了在EUV光谱区域的高光谱相干成像,而不需要基于硬件的波长分离。这种新的光谱显微镜方案是最有效地利用EUV光子进行成像,因为没有镜子或单色光学系统的能量损失。来自桌面高谐波源的EUV光谱梳,以波长30nm为中心照射样品,散射光在像素阵列探测器上收集。使用无透镜成像技术,称为ptychographic信息复用,我们同时检索图像的光谱响应的样品在每个单独的谐波。结果表明,反演的谱幅和相位与理论预测一致。这项工作证明了相干EUV光束在纳米级分辨率下快速识别材料的能力。
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引用次数: 1
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SPIE Advanced Lithography
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