A. Baca, J. Zolper, M. Sherwin, P. Robertson, R. Shul, A. J. Howard, D. Rieger, J. Klem
{"title":"互补砷化镓结门控异质结构场效应晶体管技术","authors":"A. Baca, J. Zolper, M. Sherwin, P. Robertson, R. Shul, A. J. Howard, D. Rieger, J. Klem","doi":"10.1109/GAAS.1994.636920","DOIUrl":null,"url":null,"abstract":"The first circuit results for a new GaAs complementary logic technology are presented. The technology allows for independently optimizable p- and nchannel transistors with junction gates. Excellent loaded gate delays of 179 ps at 1.2 V and 319 ps at 0.8 V have been demonstrated at low power supply voltages. A power-delay product of 8.9 fJ was obtained at 0.8 V.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"40 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"Complementary GaAs junction-gated heterostructure field effect transistor technology\",\"authors\":\"A. Baca, J. Zolper, M. Sherwin, P. Robertson, R. Shul, A. J. Howard, D. Rieger, J. Klem\",\"doi\":\"10.1109/GAAS.1994.636920\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The first circuit results for a new GaAs complementary logic technology are presented. The technology allows for independently optimizable p- and nchannel transistors with junction gates. Excellent loaded gate delays of 179 ps at 1.2 V and 319 ps at 0.8 V have been demonstrated at low power supply voltages. A power-delay product of 8.9 fJ was obtained at 0.8 V.\",\"PeriodicalId\":328819,\"journal\":{\"name\":\"Proceedings of 1994 IEEE GaAs IC Symposium\",\"volume\":\"40 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 1994 IEEE GaAs IC Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/GAAS.1994.636920\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1994 IEEE GaAs IC Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GAAS.1994.636920","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Complementary GaAs junction-gated heterostructure field effect transistor technology
The first circuit results for a new GaAs complementary logic technology are presented. The technology allows for independently optimizable p- and nchannel transistors with junction gates. Excellent loaded gate delays of 179 ps at 1.2 V and 319 ps at 0.8 V have been demonstrated at low power supply voltages. A power-delay product of 8.9 fJ was obtained at 0.8 V.
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