ATPG for 2D/3D wider Kogge-Stone Adder circuit

It is an well established fact that 3D design has a number of benefits over corresponding 2D design, albeit with somewhat more design complexity. One key advantage is the reduced set of Test Vectors needed to test a 3D circuit as the design is spread over multiple planes, each plane having reduced size than the original design. When all the TVs across these layers are combined we still get a smaller set as the TV complexity increases super linearly with the size of the circuit. In this paper we designed 4-, 8-, 16-, 32- and 64-bit 2D KSA adder circuits. We created the 3D version of the corresponding KSA circuits using two planes, inserting necessary control points in the form of Scan flip-flops. We then used TetraMax to create ATPG set of Test Vectors for these circuits to detect stuck at and transition faults. We find that the 3D version enables us to use effectively a much reduced set of Test Vectors for pre-bond testing compared to the 2D counterpart at the same time with increasing fault coverage. This is in confirmation with some of the results published in the literature on this.