Design Exploration and Scalability Analysis of a CMOS-Integrated, Polymorphic, Nanophotonic Arithmetic-Logic Unit

Over the past two decades, the clock speed, and hence, the singlecore performance of microprocessors has already stagnated. Following this, the recent faltering of Moore's law due to the CMOS fabrication technology reaching its unavoidable physical limit has presaged daunting challenges for designing power-efficient and ultrafast microprocessors. To overcome these challenges, vigorous efforts have been made to develop new more-than-Moore technologies and architectures for computing. Among these, nanophotonic integrated circuits based computing architectures have shown revolutionary potential. Among recent demonstrations of nanophotonic circuits for computing, a polymorphic, nanophotonic ALU (PoN-ALU) carries a notable importance since it has shown very high flexibility, high speed, and low power consumption for computing. In this paper, we carry out a design space exploration of this PoN-ALU to derive new design guidelines that can help scale the speed and energy efficiency of PoNALU even further.