Kyomin Sohn, Sungdae Choi, Jeong-Ho Woo, Joo-Young Kim, H. Yoo
{"title":"用于超低功耗SoC的0.6 v, 6.8 μ w嵌入式SRAM","authors":"Kyomin Sohn, Sungdae Choi, Jeong-Ho Woo, Joo-Young Kim, H. Yoo","doi":"10.1109/ASSCC.2006.357914","DOIUrl":null,"url":null,"abstract":"A novel embedded SRAM is proposed with features of high reliability and low power consumption. The critical control signals are made in correspondence to clock-duty cycle for high reliability. A hybrid precharge scheme is adopted for low power consumption. Additionally, an asymmetric read-write scheme is useful in a slow-but-steady write situation such as a control SoC for BSN (body sensor network). The fabricated 128-kb embedded SRAM consumes 117-μW at the worst case and 6.8-μW at normal write operation in a 0.6-V supply voltage.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 0.6-V, 6.8-μW Embedded SRAM for Ultra-low Power SoC\",\"authors\":\"Kyomin Sohn, Sungdae Choi, Jeong-Ho Woo, Joo-Young Kim, H. Yoo\",\"doi\":\"10.1109/ASSCC.2006.357914\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel embedded SRAM is proposed with features of high reliability and low power consumption. The critical control signals are made in correspondence to clock-duty cycle for high reliability. A hybrid precharge scheme is adopted for low power consumption. Additionally, an asymmetric read-write scheme is useful in a slow-but-steady write situation such as a control SoC for BSN (body sensor network). The fabricated 128-kb embedded SRAM consumes 117-μW at the worst case and 6.8-μW at normal write operation in a 0.6-V supply voltage.\",\"PeriodicalId\":142478,\"journal\":{\"name\":\"2006 IEEE Asian Solid-State Circuits Conference\",\"volume\":\"33 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-11-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE Asian Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2006.357914\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2006.357914","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 0.6-V, 6.8-μW Embedded SRAM for Ultra-low Power SoC
A novel embedded SRAM is proposed with features of high reliability and low power consumption. The critical control signals are made in correspondence to clock-duty cycle for high reliability. A hybrid precharge scheme is adopted for low power consumption. Additionally, an asymmetric read-write scheme is useful in a slow-but-steady write situation such as a control SoC for BSN (body sensor network). The fabricated 128-kb embedded SRAM consumes 117-μW at the worst case and 6.8-μW at normal write operation in a 0.6-V supply voltage.
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