DDR5设计挑战

2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI) Pub Date : 2018-05-22 DOI:10.1109/SAPIW.2018.8401666

B. Nitin, W. Randy, Ikeda Shinichiro, Fujine Eiji, Ryouichi Shibata, Sugaya Yumiko, Ono Megumi

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引用次数: 10

摘要

对于多插槽设置来说，以仅2666MT/s的速度操作DDR4内存通道可能是一个挑战。那么，下一代DDR5内存总线需要什么才能使它们以3200MT/s或更高的速度运行呢?控制器的含义是什么?如何为给定的控制器规划受支持的拓扑?

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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DDR5 design challenges

Operating a DDR4 memory channel at speeds of only 2666MT/s can be a challenge for multi-slot setups. So what will be required in the next-generation DDR5 memory busses to enable them to run at speeds of 3200MT/s and above? What are the implications for controllers, and how does one plan the supported topologies for a given controller?

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2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI)

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