准线性复杂度混合信号集成电路的可变性感知可靠性仿真

Elie Maricau, G. Gielen
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引用次数: 18

摘要

本文提出了一种确定性的、可变性感知的可靠性建模与仿真方法。该方法的目的是有效地模拟电路在模级应力作用下的失效时间色散。采用拟线性复杂度的实验设计(DoE)方法建立了时变电路特性的响应面模型。与随机抽样技术相比,这减少了模拟时间,并保证了电路因子空间的良好覆盖。DoE包括线性筛选设计,用于过滤掉重要的电路因素,然后是分辨率为5的分数因子回归设计,以模拟电路行为。该方法在广泛的模拟和数字电路中进行了验证,并与传统的随机抽样可靠性仿真技术进行了比较。它被证明优于现有的模拟器,仿真速度提高了几个数量级。此外,它被证明具有良好的仿真精度,在所有测试电路中,平均模型误差从1.5%到5%不等。
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Variability-aware reliability simulation of mixed-signal ICs with quasi-linear complexity
This paper demonstrates a deterministic, variability-aware reliability modeling and simulation method. The purpose of the method is to efficiently simulate failure-time dispersion in circuits subjected to die-level stress effects. A Design of Experiments (DoE) with a quasi-linear complexity is used to build a Response Surface Model (RSM) of the time-dependent circuit behavior. This reduces simulation time, when compared to random-sampling techniques, and guarantees good coverage of the circuit factor space. The DoE consists of a linear screening design, to filter out important circuit factors, followed by a resolution 5 fractional factorial regression design to model the circuit behavior. The method is validated over a broad range of both analog and digital circuits and compared to traditional random-sampling reliability simulation techniques. It is shown to outperform existing simulators with a simulation speed improvement of up to several orders of magnitude. Also, it is proven to have a good simulation accuracy, with an average model error varying from 1.5 to 5 % over all test circuits.
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