W. Prost, U. Auer, F. Tegude, C. Pacha, K. Goser, R. Duschl, K. Eberl, O. Schmidt
{"title":"隧穿二极管技术","authors":"W. Prost, U. Auer, F. Tegude, C. Pacha, K. Goser, R. Duschl, K. Eberl, O. Schmidt","doi":"10.1109/ISMVL.2001.924554","DOIUrl":null,"url":null,"abstract":"The technology of quantum tunnelling devices, namely III/V double barrier Resonant Tunnelling Diodes (RTD) and Si/SiGe Interband Tunnelling Diodes (ITD), is studied for logic circuit applications. The homogeneity and reproducibility of MBE grown InP-based RTD devices with mesa technology is presented. Si/SiGe ITD have been grown by MBE on high resistivity (n-) Silicon substrates. A novel self-aligned diode is processed using optical lithography and dopant-selective wet chemical etching. Comparing RTD and ITD data the differences are due to the vertical spacing of the doped layers within the device. A nanoelectronic circuit architecture based on an improved MOBILE threshold logic gate is used. SPICE simulations are carried-out in order to evaluate tolerable clock and supply voltage fluctuations in comparison to device fluctuations.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Tunnelling diode technology\",\"authors\":\"W. Prost, U. Auer, F. Tegude, C. Pacha, K. Goser, R. Duschl, K. Eberl, O. Schmidt\",\"doi\":\"10.1109/ISMVL.2001.924554\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The technology of quantum tunnelling devices, namely III/V double barrier Resonant Tunnelling Diodes (RTD) and Si/SiGe Interband Tunnelling Diodes (ITD), is studied for logic circuit applications. The homogeneity and reproducibility of MBE grown InP-based RTD devices with mesa technology is presented. Si/SiGe ITD have been grown by MBE on high resistivity (n-) Silicon substrates. A novel self-aligned diode is processed using optical lithography and dopant-selective wet chemical etching. Comparing RTD and ITD data the differences are due to the vertical spacing of the doped layers within the device. A nanoelectronic circuit architecture based on an improved MOBILE threshold logic gate is used. SPICE simulations are carried-out in order to evaluate tolerable clock and supply voltage fluctuations in comparison to device fluctuations.\",\"PeriodicalId\":297353,\"journal\":{\"name\":\"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic\",\"volume\":\"41 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-05-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISMVL.2001.924554\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.2001.924554","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The technology of quantum tunnelling devices, namely III/V double barrier Resonant Tunnelling Diodes (RTD) and Si/SiGe Interband Tunnelling Diodes (ITD), is studied for logic circuit applications. The homogeneity and reproducibility of MBE grown InP-based RTD devices with mesa technology is presented. Si/SiGe ITD have been grown by MBE on high resistivity (n-) Silicon substrates. A novel self-aligned diode is processed using optical lithography and dopant-selective wet chemical etching. Comparing RTD and ITD data the differences are due to the vertical spacing of the doped layers within the device. A nanoelectronic circuit architecture based on an improved MOBILE threshold logic gate is used. SPICE simulations are carried-out in order to evaluate tolerable clock and supply voltage fluctuations in comparison to device fluctuations.