H. Yun, Gang Yao, R. Pellizzoni, M. Caccamo, L. Sha
{"title":"混合临界实时系统的多处理器存储器访问控制","authors":"H. Yun, Gang Yao, R. Pellizzoni, M. Caccamo, L. Sha","doi":"10.1109/ECRTS.2012.32","DOIUrl":null,"url":null,"abstract":"Shared resource access interference, particularly memory and system bus, is a big challenge in designing predictable real-time systems because its worst case behavior can significantly differ. In this paper, we propose a software based memory throttling mechanism to explicitly control the memory interference. We developed analytic solutions to compute proper throttling parameters that satisfy schedulability of critical tasks while minimize performance impact caused by throttling. We implemented the mechanism in Linux kernel and evaluated isolation guarantee and overall performance impact using a set of synthetic and real applications.","PeriodicalId":425794,"journal":{"name":"2012 24th Euromicro Conference on Real-Time Systems","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"146","resultStr":"{\"title\":\"Memory Access Control in Multiprocessor for Real-Time Systems with Mixed Criticality\",\"authors\":\"H. Yun, Gang Yao, R. Pellizzoni, M. Caccamo, L. Sha\",\"doi\":\"10.1109/ECRTS.2012.32\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Shared resource access interference, particularly memory and system bus, is a big challenge in designing predictable real-time systems because its worst case behavior can significantly differ. In this paper, we propose a software based memory throttling mechanism to explicitly control the memory interference. We developed analytic solutions to compute proper throttling parameters that satisfy schedulability of critical tasks while minimize performance impact caused by throttling. We implemented the mechanism in Linux kernel and evaluated isolation guarantee and overall performance impact using a set of synthetic and real applications.\",\"PeriodicalId\":425794,\"journal\":{\"name\":\"2012 24th Euromicro Conference on Real-Time Systems\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-07-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"146\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 24th Euromicro Conference on Real-Time Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ECRTS.2012.32\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 24th Euromicro Conference on Real-Time Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECRTS.2012.32","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Memory Access Control in Multiprocessor for Real-Time Systems with Mixed Criticality
Shared resource access interference, particularly memory and system bus, is a big challenge in designing predictable real-time systems because its worst case behavior can significantly differ. In this paper, we propose a software based memory throttling mechanism to explicitly control the memory interference. We developed analytic solutions to compute proper throttling parameters that satisfy schedulability of critical tasks while minimize performance impact caused by throttling. We implemented the mechanism in Linux kernel and evaluated isolation guarantee and overall performance impact using a set of synthetic and real applications.