One Clock-Cycle Response 0.5 m CMOS Dual-Mode ΣΔ DC-DC Bypass Boost Converter Stable over Wide ESRLC Variations

Power supplies in portable applications must not only conform and adapt to their highly integrated on-chip and in-package environments but also, more intrinsically, respond quickly to fast load dumps to achieve and maintain high accuracy. The frequency-compensation network, however, limits speed and regulation performance because it must cater to all combinations of filter capacitor 𝐶 𝑂 , inductor L, and 𝐶 𝑂 's equivalent series resistance 𝑅 E S R resulting from tolerance and modal design targets. As such, it must compensate the worst-case condition and therefore restrain the performance of all other possible scenarios, even if the likelihood of occurrence of the latter is considerably high and the former substantially low. Sigma-delta ( Σ Δ ) control, which addresses this issue in buck converters by easing its compensation requirements and offering one-cycle transient response, has not been able to simultaneously achieve high bandwidth, high accuracy, and wide 𝑅 E S R L C compliance in boost converters. This paper presents a dual-mode Σ Δ boost bypass converter, which by using a high-bandwidth bypass path only during transient load-dump events was experimentally 1.41 to 6 times faster than the state of the art in current-mode Σ Δ boost supplies, and this without any compromise in 𝑅 E S R L C compliance range (0–50 m Ω , 1–30  𝜇 H, and 1–350  𝜇 F).