A digit-recurrence square root implementation for field programmable gate arrays

Creating efficient arithmetic processors requires a pairing of high speed arithmetic algorithms with optimal mapping strategies for a given technology. The authors propose bit reduction as key to an efficient pairing process for lookup table based field programmable gate arrays (FPGAs). Bit reduction simplifies the functions defining the original algorithm, thus permitting a mapping to fewer blocks and reducing the overall throughput delay. A mapping of a digit-recurrence square root algorithm to the Xilinx XC4010 FPGA illustrates the bit reduction process.<>