A framework for the design of reconfigurable fault tolerant architectures

The rapid evolutions in reconfigurable electronic products design permit to handle more and more complex applications. New fields of investigations (i.e. automotive, aerospatial, banking,…) are interesting but require a high level of dependability. This paper proposes a framework to design reconfig-urable architecture supporting fault-tolerance mitigation scheme. The proposed framework allows simulation, validation of mitigation operations, but also to size architecture resources. The implementation of a fault-tolerant reconfigurable platform permits to validate the proposed model and the effectiveness of the framework. This implementation shows the potential of dynamically reconfigurable architectures for supporting fault-tolerance in embedded systems.