Pub Date : 2011-11-02DOI: 10.1109/DASIP.2011.6136850
Nicolas Siret, J. Nezan, Aimad Rhatay
Heterogeneous platforms aim to offer both performance and flexibility by providing designers processors and programmable logical units on a single platform. Processors implemented on these platforms are usually soft-cores (e.g. Altera NIOS) or ASIC (e.g. ARM Cortex-A8). However, these processors still face limitations in terms of performance compared to full hardware designs in particular for real-time video decoding applications. We present in this paper an innovative approach to improve performance using both a processor optimized for the syntax parsing (an Application-Specific Instruction-set Processor) and a FPGA. The case study has been synthesized on a Xilinx FPGA at a frequency of 100 MHz and we estimate the performance that could be obtained with an ASIC.
{"title":"Design of a processor optimized for syntax parsing in video decoders","authors":"Nicolas Siret, J. Nezan, Aimad Rhatay","doi":"10.1109/DASIP.2011.6136850","DOIUrl":"https://doi.org/10.1109/DASIP.2011.6136850","url":null,"abstract":"Heterogeneous platforms aim to offer both performance and flexibility by providing designers processors and programmable logical units on a single platform. Processors implemented on these platforms are usually soft-cores (e.g. Altera NIOS) or ASIC (e.g. ARM Cortex-A8). However, these processors still face limitations in terms of performance compared to full hardware designs in particular for real-time video decoding applications. We present in this paper an innovative approach to improve performance using both a processor optimized for the syntax parsing (an Application-Specific Instruction-set Processor) and a FPGA. The case study has been synthesized on a Xilinx FPGA at a frequency of 100 MHz and we estimate the performance that could be obtained with an ASIC.","PeriodicalId":199500,"journal":{"name":"Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128468132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-02DOI: 10.1109/DASIP.2011.6136848
Takieddine Majdoub, S. L. Nours, O. Pasquier, F. Nouvel
Due to increasing complexity of communication infrastructures in the automotive domain, reliable models are necessary in order to assist designers in the development process of networked embedded systems. In this context, transaction level modeling, supported by languages as SystemC, is a promising solution to assess performances of networked architectures with a good compromise between accuracy and simulation speed. This article presents the application of a specific modeling approach for performance evaluation of a networked embedded system inspired from the automotive domain. The considered approach is illustrated by the modeling of a video transmission system made of three electronic controller units and based on a specific power line communication protocol. The created model incorporates description of various communication layers and simulation of the model allows evaluation of time properties and memory cost inferred.
{"title":"Performance evaluation of an automotive distributed architecture based on HPAV communication protocol using a transaction level modeling approach","authors":"Takieddine Majdoub, S. L. Nours, O. Pasquier, F. Nouvel","doi":"10.1109/DASIP.2011.6136848","DOIUrl":"https://doi.org/10.1109/DASIP.2011.6136848","url":null,"abstract":"Due to increasing complexity of communication infrastructures in the automotive domain, reliable models are necessary in order to assist designers in the development process of networked embedded systems. In this context, transaction level modeling, supported by languages as SystemC, is a promising solution to assess performances of networked architectures with a good compromise between accuracy and simulation speed. This article presents the application of a specific modeling approach for performance evaluation of a networked embedded system inspired from the automotive domain. The considered approach is illustrated by the modeling of a video transmission system made of three electronic controller units and based on a specific power line communication protocol. The created model incorporates description of various communication layers and simulation of the model allows evaluation of time properties and memory cost inferred.","PeriodicalId":199500,"journal":{"name":"Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)","volume":"6 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123520796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-02DOI: 10.1109/DASIP.2011.6136899
H. Pham, S. Pillement, O. Pasquier, S. L. Nours
The rapid evolutions in reconfigurable electronic products design permit to handle more and more complex applications. New fields of investigations (i.e. automotive, aerospatial, banking,…) are interesting but require a high level of dependability. This paper proposes a framework to design reconfig-urable architecture supporting fault-tolerance mitigation scheme. The proposed framework allows simulation, validation of mitigation operations, but also to size architecture resources. The implementation of a fault-tolerant reconfigurable platform permits to validate the proposed model and the effectiveness of the framework. This implementation shows the potential of dynamically reconfigurable architectures for supporting fault-tolerance in embedded systems.
{"title":"A framework for the design of reconfigurable fault tolerant architectures","authors":"H. Pham, S. Pillement, O. Pasquier, S. L. Nours","doi":"10.1109/DASIP.2011.6136899","DOIUrl":"https://doi.org/10.1109/DASIP.2011.6136899","url":null,"abstract":"The rapid evolutions in reconfigurable electronic products design permit to handle more and more complex applications. New fields of investigations (i.e. automotive, aerospatial, banking,…) are interesting but require a high level of dependability. This paper proposes a framework to design reconfig-urable architecture supporting fault-tolerance mitigation scheme. The proposed framework allows simulation, validation of mitigation operations, but also to size architecture resources. The implementation of a fault-tolerant reconfigurable platform permits to validate the proposed model and the effectiveness of the framework. This implementation shows the potential of dynamically reconfigurable architectures for supporting fault-tolerance in embedded systems.","PeriodicalId":199500,"journal":{"name":"Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)","volume":"15 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132070195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-02DOI: 10.1109/DASIP.2011.6136852
S. Rethinagiri, R. B. Atitallah, S. Niar, E. Senn, J. Dekeyser
Nowadays, having the appropriate Electronic System Level (ESL) tools for power estimation in embedded systems is becoming mandatory. The main challenge for the design of such dedicated tools is to achieve a better trade-offs between accuracy and speed. In this paper, a new power consumption estimation methodology for embedded systems is proposed. First, the Functional Level Power Analysis (FLPA) is used to set up generic power models based on real board measurements. In the second step, a simulation framework is developed to evaluate accurately the architectural parameters of the elaborated power models. The proposed methodology has several benefits: it improves significantly the accuracy of the functional level approach and the power consumption estimation can be accomplished without a costly and complex material. In order to speed up the estimation process, our methodology refers to the selection of data pattern size and to the application sampling technique. Experimental results show that our tool achieves high simulation speed of 21 times faster with a marginal power estimation error of 1%.
{"title":"Fast and accurate hybrid power estimation methodology for embedded systems","authors":"S. Rethinagiri, R. B. Atitallah, S. Niar, E. Senn, J. Dekeyser","doi":"10.1109/DASIP.2011.6136852","DOIUrl":"https://doi.org/10.1109/DASIP.2011.6136852","url":null,"abstract":"Nowadays, having the appropriate Electronic System Level (ESL) tools for power estimation in embedded systems is becoming mandatory. The main challenge for the design of such dedicated tools is to achieve a better trade-offs between accuracy and speed. In this paper, a new power consumption estimation methodology for embedded systems is proposed. First, the Functional Level Power Analysis (FLPA) is used to set up generic power models based on real board measurements. In the second step, a simulation framework is developed to evaluate accurately the architectural parameters of the elaborated power models. The proposed methodology has several benefits: it improves significantly the accuracy of the functional level approach and the power consumption estimation can be accomplished without a costly and complex material. In order to speed up the estimation process, our methodology refers to the selection of data pattern size and to the application sampling technique. Experimental results show that our tool achieves high simulation speed of 21 times faster with a marginal power estimation error of 1%.","PeriodicalId":199500,"journal":{"name":"Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)","volume":"252 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132677578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-02DOI: 10.1109/DASIP.2011.6136863
M. Hentati, Y. Aoudni, J. Nezan, Mohamed Abid, O. Déforges
With the rapid evolution of technology, the latest FPGA architectures such as Virtex series of Xilinx introduced a new feature called Dynamic Partial Reconfiguration (DPR). This technique allows designer to configure a portion of the FPGA while other parts continue to run on the same FPGA. The design of an embedded system based on the DPR functionality is still complex and tedious. The MPEG consortium proposes the Reconfigurable Video Coding (RVC) technology. RVC provides a high level description of video decoders described as a set of interconnected Functional Units. This paper studies the use of the RVC technology for the specification of an application and the design of a system based on the DPR functionality. In this paper, we study the Inverse Quantization (IQ) algorithm of an MPEG-4 decoder and how to switch between the MPEG-2 and the H263 IQ algorithms using RVC and DPR. This simple and concrete case study highlights the DPR restrictions to take into account in MPEG RVC description in order to use the DPR.
{"title":"FPGA dynamic reconfiguration using the RVC technology: Inverse quantization case study","authors":"M. Hentati, Y. Aoudni, J. Nezan, Mohamed Abid, O. Déforges","doi":"10.1109/DASIP.2011.6136863","DOIUrl":"https://doi.org/10.1109/DASIP.2011.6136863","url":null,"abstract":"With the rapid evolution of technology, the latest FPGA architectures such as Virtex series of Xilinx introduced a new feature called Dynamic Partial Reconfiguration (DPR). This technique allows designer to configure a portion of the FPGA while other parts continue to run on the same FPGA. The design of an embedded system based on the DPR functionality is still complex and tedious. The MPEG consortium proposes the Reconfigurable Video Coding (RVC) technology. RVC provides a high level description of video decoders described as a set of interconnected Functional Units. This paper studies the use of the RVC technology for the specification of an application and the design of a system based on the DPR functionality. In this paper, we study the Inverse Quantization (IQ) algorithm of an MPEG-4 decoder and how to switch between the MPEG-2 and the H263 IQ algorithms using RVC and DPR. This simple and concrete case study highlights the DPR restrictions to take into account in MPEG RVC description in order to use the DPR.","PeriodicalId":199500,"journal":{"name":"Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126218886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/DASIP.2011.6136870
Matthieu Texier, E. Piriou, M. Thévenin, R. David
As application complexity increases, the design of efficient computing architectures able to cope with embedded constraints requires a fine algorithm analysis. This paper proposes an original approach based on Modular Assembly Simulator (MAsS) tool that allows Design Space Exploration (DSE) for programmable processors. The originality of the method resides in its capacity to generate operator level simulators allowing a quick code analysis from real data sets. This paper also presents two successfully designed architectures using MAsS.
{"title":"Designing processors using MAsS, a modular and lightweight instruction-level exploration tool","authors":"Matthieu Texier, E. Piriou, M. Thévenin, R. David","doi":"10.1109/DASIP.2011.6136870","DOIUrl":"https://doi.org/10.1109/DASIP.2011.6136870","url":null,"abstract":"As application complexity increases, the design of efficient computing architectures able to cope with embedded constraints requires a fine algorithm analysis. This paper proposes an original approach based on Modular Assembly Simulator (MAsS) tool that allows Design Space Exploration (DSE) for programmable processors. The originality of the method resides in its capacity to generate operator level simulators allowing a quick code analysis from real data sets. This paper also presents two successfully designed architectures using MAsS.","PeriodicalId":199500,"journal":{"name":"Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128697547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/DASIP.2011.6136880
N. Frietsch, I. Pashkovskiy, G. Trommer, L. Braun, M. Birk, M. Hübner, J. Becker
In this paper, the development of the vision based motion estimation for a small-scale VTOL-MAV as well as the implementation on FPGA are investigated. Especially in urban environments the GPS signal quality is disturbed by shading and multipath propagation and an augmentation with another sensor is inevitable. The vision system bases on the analysis of the sparse optical flow that is extracted from images taken by the onboard camera. From the extracted point correspondences projective transformations are estimated with a robust parameter estimation algorithm. As the underlying image processing routines are computationally expensive but can be processed in parallel they have been implemented on FPGA. The different parts of the algorithm as well as the implementation are covered in detail.
{"title":"Development of a method for image-based motion estimation of a VTOL-MAV on FPGA","authors":"N. Frietsch, I. Pashkovskiy, G. Trommer, L. Braun, M. Birk, M. Hübner, J. Becker","doi":"10.1109/DASIP.2011.6136880","DOIUrl":"https://doi.org/10.1109/DASIP.2011.6136880","url":null,"abstract":"In this paper, the development of the vision based motion estimation for a small-scale VTOL-MAV as well as the implementation on FPGA are investigated. Especially in urban environments the GPS signal quality is disturbed by shading and multipath propagation and an augmentation with another sensor is inevitable. The vision system bases on the analysis of the sparse optical flow that is extracted from images taken by the onboard camera. From the extracted point correspondences projective transformations are estimated with a robust parameter estimation algorithm. As the underlying image processing routines are computationally expensive but can be processed in parallel they have been implemented on FPGA. The different parts of the algorithm as well as the implementation are covered in detail.","PeriodicalId":199500,"journal":{"name":"Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116205166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/DASIP.2011.6136872
J. Ayoub, B. Granado, O. Romain, Y. Mohanna
This paper describes a novel approach to capsular endoscopy that takes advantage of existing wireless capsule endoscopy (WCE) and overcomes some of its important limits. The basic and essential task concerning the integration of SVM classifier is listed and discussed in details, as well as the new features required to improve its diagnostic capability. In addition, a large scale demonstrator has been evaluated and tested. In vitro experimental results were encouraging and show correct classification rate of intestinal polyps of approximately 93.7%. The work contains detailed statistics about the detection rate and the computing complexity.
{"title":"A new approach to 3D form recognition within video capsule endoscopic","authors":"J. Ayoub, B. Granado, O. Romain, Y. Mohanna","doi":"10.1109/DASIP.2011.6136872","DOIUrl":"https://doi.org/10.1109/DASIP.2011.6136872","url":null,"abstract":"This paper describes a novel approach to capsular endoscopy that takes advantage of existing wireless capsule endoscopy (WCE) and overcomes some of its important limits. The basic and essential task concerning the integration of SVM classifier is listed and discussed in details, as well as the new features required to improve its diagnostic capability. In addition, a large scale demonstrator has been evaluated and tested. In vitro experimental results were encouraging and show correct classification rate of intestinal polyps of approximately 93.7%. The work contains detailed statistics about the detection rate and the computing complexity.","PeriodicalId":199500,"journal":{"name":"Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132315037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/DASIP.2011.6136889
C. Condo, G. Masera
The need for efficient and flexible LDPC (Low Density parity Check) code decoders is rising due to the growing number and variety of standards that adopt this kind of error correcting codes in wireless applications. From the implementation point of view, the decoding of LDPC codes implies intensive computation and communication among hardware components. These processing capabilities are usually obtained by allocating a sufficient number of processing elements (PEs) and proper interconnect structures. In this paper, Network on Chip (NoC) concepts are applied to the design of a fully flexible decoder, capable to support any LDPC code with no constraints on code structure. It is shown that NoC based decoders also achieve relevant throughput values, comparable to those obtained by several specialized decoders. Moreover, the paper explores the area and power overhead introduced by the NoC approach. In particular, two methods are proposed to reduce the traffic injected in the network during the decoding process, namely early stopping of iterations and message stopping. These methods are usually adopted to increase throughput. On the contrary, in this paper, we leverage iteration and message stopping to cut the area and power overhead of NoC based decoders. It is shown that, by reducing the traffic injected in the NoC and the number of iterations performed by the decoding algorithm, the decoder can be scaled to lower degrees of parallelism with small losses in terms of BER (Bit Error Rate) performance. VLSI synthesis results on a 130 nm technology show up to 50% area and energy reduction while maintaining an almost constant throughput.
{"title":"A flexible NoC-based LDPC code decoder implementation and bandwidth reduction methods","authors":"C. Condo, G. Masera","doi":"10.1109/DASIP.2011.6136889","DOIUrl":"https://doi.org/10.1109/DASIP.2011.6136889","url":null,"abstract":"The need for efficient and flexible LDPC (Low Density parity Check) code decoders is rising due to the growing number and variety of standards that adopt this kind of error correcting codes in wireless applications. From the implementation point of view, the decoding of LDPC codes implies intensive computation and communication among hardware components. These processing capabilities are usually obtained by allocating a sufficient number of processing elements (PEs) and proper interconnect structures. In this paper, Network on Chip (NoC) concepts are applied to the design of a fully flexible decoder, capable to support any LDPC code with no constraints on code structure. It is shown that NoC based decoders also achieve relevant throughput values, comparable to those obtained by several specialized decoders. Moreover, the paper explores the area and power overhead introduced by the NoC approach. In particular, two methods are proposed to reduce the traffic injected in the network during the decoding process, namely early stopping of iterations and message stopping. These methods are usually adopted to increase throughput. On the contrary, in this paper, we leverage iteration and message stopping to cut the area and power overhead of NoC based decoders. It is shown that, by reducing the traffic injected in the NoC and the number of iterations performed by the decoding algorithm, the decoder can be scaled to lower degrees of parallelism with small losses in terms of BER (Bit Error Rate) performance. VLSI synthesis results on a 130 nm technology show up to 50% area and energy reduction while maintaining an almost constant throughput.","PeriodicalId":199500,"journal":{"name":"Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130031092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/DASIP.2011.6136897
François Duhem, F. Muller, P. Lorenzini
As a matter of fact, there is a lack of tools handling partially reconfigurable FPGAs modeling at a high level of abstraction that give sufficient degree of freedom to the designer for testing scheduling algorithms. In this paper, we present our methodology to fill this gap and take into account partial reconfiguration into high-level modeling with SystemC. Our approach relies on dynamic threads to change the functionality of modules during runtime and on transaction level modeling for all the communications. We introduce a reconfiguration manager to develop and validate scheduling algorithms for hardware tasks management. Moreover, our simulator performs design space exploration in order to find a viable implementation (in terms of reconfigurable zones) for a given application. Our methodology is validated with the modeling of a dynamically reconfigurable video transcoding chain.
{"title":"Methodology for designing partially reconfigurable systems using transaction-level modeling","authors":"François Duhem, F. Muller, P. Lorenzini","doi":"10.1109/DASIP.2011.6136897","DOIUrl":"https://doi.org/10.1109/DASIP.2011.6136897","url":null,"abstract":"As a matter of fact, there is a lack of tools handling partially reconfigurable FPGAs modeling at a high level of abstraction that give sufficient degree of freedom to the designer for testing scheduling algorithms. In this paper, we present our methodology to fill this gap and take into account partial reconfiguration into high-level modeling with SystemC. Our approach relies on dynamic threads to change the functionality of modules during runtime and on transaction level modeling for all the communications. We introduce a reconfiguration manager to develop and validate scheduling algorithms for hardware tasks management. Moreover, our simulator performs design space exploration in order to find a viable implementation (in terms of reconfigurable zones) for a given application. Our methodology is validated with the modeling of a dynamically reconfigurable video transcoding chain.","PeriodicalId":199500,"journal":{"name":"Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)","volume":"2527 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128654596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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