{"title":"可扩展嵌入式雷达信号处理器的硬件/软件协同设计","authors":"Charles W. Buenzli, L. Owen, F. Rose","doi":"10.1109/VIUF.1997.623951","DOIUrl":null,"url":null,"abstract":"The RASSP performance modeling methodology was used to rapidly model and compare alternative hardware/software architectures for a scalable embedded radar signal processor based on COTS DSP boards. VHDL performance models were generated from graphical hardware and software architectures using Cosmos/sup TM/, simulated with QuickHDL/sup TM/, and analyzed with Cosmos. Results for a Mercury RACEway/sup TM/ architecture are presented.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Hardware/software codesign of a scalable embedded radar signal processor\",\"authors\":\"Charles W. Buenzli, L. Owen, F. Rose\",\"doi\":\"10.1109/VIUF.1997.623951\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The RASSP performance modeling methodology was used to rapidly model and compare alternative hardware/software architectures for a scalable embedded radar signal processor based on COTS DSP boards. VHDL performance models were generated from graphical hardware and software architectures using Cosmos/sup TM/, simulated with QuickHDL/sup TM/, and analyzed with Cosmos. Results for a Mercury RACEway/sup TM/ architecture are presented.\",\"PeriodicalId\":212876,\"journal\":{\"name\":\"Proceedings VHDL International Users' Forum. Fall Conference\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-10-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings VHDL International Users' Forum. Fall Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VIUF.1997.623951\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings VHDL International Users' Forum. Fall Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VIUF.1997.623951","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Hardware/software codesign of a scalable embedded radar signal processor
The RASSP performance modeling methodology was used to rapidly model and compare alternative hardware/software architectures for a scalable embedded radar signal processor based on COTS DSP boards. VHDL performance models were generated from graphical hardware and software architectures using Cosmos/sup TM/, simulated with QuickHDL/sup TM/, and analyzed with Cosmos. Results for a Mercury RACEway/sup TM/ architecture are presented.
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