A 3-ghz 25-mw Cmos Phase-locked Loop

The demand for high-speed, low-power communication circuits has dramatically grown over the past few years. Potential markets from powerful personal communicators to wireless ATM systems have stimulated great effort in reducing the supply voltage and power dissipation of gigahertz circuits. In this respect, deep submicron CMOS technologies have become contenders to 111-V and silicon bipolar devices because they offer the speed, density, and power required for such applications. This paper describes the design of a 3-GHz phase-locked loop (PLL) fabricated in a partially-scaled 0.1-pm bulk CMOS technology [l]. The circuit employs a number of techniques to allow operation from a low supply voltage and overcome the limitations due to device layout rules described below. In order to improve the yield and reduce the turnaround time and cost, the CMOS process used here scales only the channel