一个2.5GHz, 30mW, 0.03mm2，全数字延迟锁定环路

2006 IEEE Asian Solid-State Circuits Conference Pub Date : 2006-11-01 DOI:10.1109/ASSCC.2006.357903

Rong-Jyi Yang, Shen-Iuan Liu

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摘要

A.提出了一种基于0.13 μ m CMOS技术的2.5GHz、30mW、0.03mm2全数字DLL。晶格延迟单元提供了两个NAND门的小延迟步长和固定的固有延迟。修改后的二进制搜索控制器减少了锁定时间，并允许DLL跟踪PVT的变化。该DLL锁定24个周期，具有14ps的pk-pk抖动的闭环特性。

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A 2.5GHz, 30mW, 0.03mm2, All-Digital Delay-Locked Loop

A. 2.5GHz, 30mW, 0.03mm2, all-digital DLL in 0.13mum CMOS technology is presented. The lattice delay unit provides both a small delay step and a fixed intrinsic delay of two NAND gates. A modified binary search controller reduces the locking time and allows the DLL to track the PVT variations. This DLL locks in 24 cycles and has the closed-loop characteristic with pk-pk jitter of 14ps.

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2006 IEEE Asian Solid-State Circuits Conference

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