Design of a time-based capacitance-to-digital converter using current starved inverters

This paper presents a new design methodology of time-based capacitance-to-digital converters (T-CDCs). The sensor capacitance is the load capacitance of a voltage-to-time converter (VTC) circuit based on current starved inverters. The VTC circuit used has improved sensitivity, linearity and dynamic range. The time delay provided by the VTC circuit is buffered providing a time pulse proportional to the sensor capacitance (Cs). Thus, the VTC circuit becomes a capacitance-to-time converter (CTC) circuit. The time pulse is then digitized using a time-to-digital converter (TDC) circuit providing an output digital code proportional to the sensor capacitance. The output digital code is PVT calibrated using a reference capacitor (Cref). The proposed T-CDC system is a time-based ADC, but with the sensor capacitance as the load capacitance of the used VTC circuit and the input voltages of the current starved inverters in the VTC circuit are fixed and used for biasing. The prototype of the proposed T-CDC is implemented in UMC 130 nm CMOS technology. The T-CDC system is clocked with a 1-MHz clock signal to the VTC circuit. Experimental results show that for a 1 ns counting cycle of the TDC circuit, the system achieves a 8.5-bit resolution and consumes 20 μW with an energy efficiency figure-of-merit (FoM) of 55 fJ/step and a conversion time of 1 μs.