Design of an 8-bit 100 KSPS 1 mW CMOS A/D converter for digital mobile communication

In this paper, an 8-bit 100 KSPS 1 mW CMOS A/D converter for digital mobile communication is proposed. The main architecture of the A/D converter is based on a cyclic type, in order to reduce power consumption. This is composed of a proposed Sample and Hold Amplifier (SHA), fully differential gain amplifier and comparator. As the proposed SHA is driven by an offset cancellation clock to reduce offset voltage, the input voltage is held accurately. The proposed fully differential gain amplifier employs a half magnitude of the input capacitance compared to that of the conventional one. Thus both the input capacitance and feedback capacitance have the same value. The A/D converter is fabricated with a 0.6 /spl mu/m single-poly triple-metal n-well CMOS technology and has a power consumption of 980 /spl mu/W at 3 V power supply. Further, the INL and DNL are within /spl plusmn/1 LSB and SNR is about 45 dB.