{"title":"一个单芯片数字电视LSI与灵活的二维图形处理器利用优化的存储器结构","authors":"M. Yamada, E. Tomonaga, M. Lin, J. Hung","doi":"10.1109/ICCE.1999.785216","DOIUrl":null,"url":null,"abstract":"A single chip digital TV LSI including MPU, transport decoder, MPEG audio/video decoder, and graphic processor is described. This LSI utilizes dedicated RISC processors and advanced unified memory architecture with special arbitration algorithm, which enables optimal memory access operation.","PeriodicalId":425143,"journal":{"name":"1999 Digest of Technical Papers. International Conference on Consumer Electronics (Cat. No.99CH36277)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A single chip digital TV LSI with a flexible 2D graphic processor utilizing an optimized memory architecture\",\"authors\":\"M. Yamada, E. Tomonaga, M. Lin, J. Hung\",\"doi\":\"10.1109/ICCE.1999.785216\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A single chip digital TV LSI including MPU, transport decoder, MPEG audio/video decoder, and graphic processor is described. This LSI utilizes dedicated RISC processors and advanced unified memory architecture with special arbitration algorithm, which enables optimal memory access operation.\",\"PeriodicalId\":425143,\"journal\":{\"name\":\"1999 Digest of Technical Papers. International Conference on Consumer Electronics (Cat. No.99CH36277)\",\"volume\":\"31 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-06-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1999 Digest of Technical Papers. International Conference on Consumer Electronics (Cat. No.99CH36277)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCE.1999.785216\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1999 Digest of Technical Papers. International Conference on Consumer Electronics (Cat. No.99CH36277)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCE.1999.785216","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A single chip digital TV LSI with a flexible 2D graphic processor utilizing an optimized memory architecture
A single chip digital TV LSI including MPU, transport decoder, MPEG audio/video decoder, and graphic processor is described. This LSI utilizes dedicated RISC processors and advanced unified memory architecture with special arbitration algorithm, which enables optimal memory access operation.
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