采用Verilog-AMS的2.4 GHz CMOS VCO设计

Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442) Pub Date : 1900-01-01 DOI:10.1109/ICM.2003.238421

Kuo-Hua Cheng, C. Jou

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引用次数: 5

摘要

Verilog-AMS语言是一种高级语言，它使用模块来描述模拟系统及其组件的结构和行为。它是IEEE 1364 Verilog硬件描述语言(HDL)的扩展。本文介绍了一种由Verilog-A公司开发的用于IP和SoC的2.4 GHz VCO模型。由台积电0.25-/spl mu/m制造;根据测量结果，调谐范围为187 MHz (7.78%);在2.4 GHz时相位噪声为91dBc/HZ@1 MHz偏移。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2.4 GHz CMOS VCO design with Verilog-AMS

The Verilog-AMS language is a high-level language that uses modules to describe the structure and behavior of analog systems and their components. It is an extension to IEEE 1364 Verilog Hardware Description Language (HDL). This paper presents a 2.4 GHz VCO model by Verilog-A for IP and SoC purpose. It fabricated by TSMC 0.25-/spl mu/m; based on the measurement results, the tuning range is 187 MHz (7.78%); phase noise is 91dBc/HZ@1 MHz offset at 2.4 GHz.

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Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)

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