{"title":"从流水线和超标量设计的正式验证中收集高级微处理器错误","authors":"M. Velev","doi":"10.1109/TEST.2003.1270834","DOIUrl":null,"url":null,"abstract":"The paper presents a collection of 93 different bugs, detected in formal verification of 65 student designs that include: 1 ) singleissue pipelined DLX processors; 2 ) extensions with exceptions and branch prediction; and 3) dual-issue superscalar implementations. The processors were described in a high-level HDL, and were formally verified with an automatic tool flow. The bugs are analyzed and classified, and can be used in research on microprocessor testing.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"121 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"29","resultStr":"{\"title\":\"Collection of high-level microprocessor bugs from formal verification of pipelined and superscalar designs\",\"authors\":\"M. Velev\",\"doi\":\"10.1109/TEST.2003.1270834\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper presents a collection of 93 different bugs, detected in formal verification of 65 student designs that include: 1 ) singleissue pipelined DLX processors; 2 ) extensions with exceptions and branch prediction; and 3) dual-issue superscalar implementations. The processors were described in a high-level HDL, and were formally verified with an automatic tool flow. The bugs are analyzed and classified, and can be used in research on microprocessor testing.\",\"PeriodicalId\":236182,\"journal\":{\"name\":\"International Test Conference, 2003. Proceedings. ITC 2003.\",\"volume\":\"121 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-09-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"29\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Test Conference, 2003. Proceedings. ITC 2003.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TEST.2003.1270834\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Test Conference, 2003. Proceedings. ITC 2003.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.2003.1270834","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Collection of high-level microprocessor bugs from formal verification of pipelined and superscalar designs
The paper presents a collection of 93 different bugs, detected in formal verification of 65 student designs that include: 1 ) singleissue pipelined DLX processors; 2 ) extensions with exceptions and branch prediction; and 3) dual-issue superscalar implementations. The processors were described in a high-level HDL, and were formally verified with an automatic tool flow. The bugs are analyzed and classified, and can be used in research on microprocessor testing.
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