{"title":"一个新的语言套件，用于设计人员指定的ASIC单元编译器","authors":"S. Purcell, M. Handa, R. L. Steinweg","doi":"10.1109/ASIC.1989.123182","DOIUrl":null,"url":null,"abstract":"An integrated set of design languages is presented for describing the various outputs of a cell compiler within VLSI Technology's ASIC (application-specific integrated circuit) design tool environment. The outputs include physical layout, netlists of several types, various external attributes of the compiled cell, and test vectors. The languages were designed with the goal of being simple enough to enable software-inexperienced circuit designers to create complex cell compilers independently. The languages, which follow a consistent format and use intuitive constructs, increase compiler development productivity significantly, primarily by removing the software engineer from the compiler development tool.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A new language suite for designer-specifiable ASIC cell compilers\",\"authors\":\"S. Purcell, M. Handa, R. L. Steinweg\",\"doi\":\"10.1109/ASIC.1989.123182\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An integrated set of design languages is presented for describing the various outputs of a cell compiler within VLSI Technology's ASIC (application-specific integrated circuit) design tool environment. The outputs include physical layout, netlists of several types, various external attributes of the compiled cell, and test vectors. The languages were designed with the goal of being simple enough to enable software-inexperienced circuit designers to create complex cell compilers independently. The languages, which follow a consistent format and use intuitive constructs, increase compiler development productivity significantly, primarily by removing the software engineer from the compiler development tool.<<ETX>>\",\"PeriodicalId\":245997,\"journal\":{\"name\":\"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-09-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1989.123182\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1989.123182","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A new language suite for designer-specifiable ASIC cell compilers
An integrated set of design languages is presented for describing the various outputs of a cell compiler within VLSI Technology's ASIC (application-specific integrated circuit) design tool environment. The outputs include physical layout, netlists of several types, various external attributes of the compiled cell, and test vectors. The languages were designed with the goal of being simple enough to enable software-inexperienced circuit designers to create complex cell compilers independently. The languages, which follow a consistent format and use intuitive constructs, increase compiler development productivity significantly, primarily by removing the software engineer from the compiler development tool.<>
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