{"title":"采用0.18µm CMOS技术有源电阻的超宽带LNA设计","authors":"S. Nigam, P. C. Sau","doi":"10.1109/CCINTELS.2015.7437947","DOIUrl":null,"url":null,"abstract":"The proposed design of LNA uses common gate topology as an amplifying section. Noise cancelling technique is used and special emphasis is laid on the use of active resistors so that overall Noise figure is minimized and gain is enhanced. Simulation is done on ADS tool using 0.18μm technology. Power supply provided is 1.8V. Maximum gain achieved is 14.774dB. Noise figure achieved is 1dB to 1.6 dB over entire bandwidth. Bandwidth achieved is 3-9GHz.","PeriodicalId":131816,"journal":{"name":"2015 Communication, Control and Intelligent Systems (CCIS)","volume":"7 3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Design of UWB LNA using active resistors in 0.18µm CMOS technology\",\"authors\":\"S. Nigam, P. C. Sau\",\"doi\":\"10.1109/CCINTELS.2015.7437947\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The proposed design of LNA uses common gate topology as an amplifying section. Noise cancelling technique is used and special emphasis is laid on the use of active resistors so that overall Noise figure is minimized and gain is enhanced. Simulation is done on ADS tool using 0.18μm technology. Power supply provided is 1.8V. Maximum gain achieved is 14.774dB. Noise figure achieved is 1dB to 1.6 dB over entire bandwidth. Bandwidth achieved is 3-9GHz.\",\"PeriodicalId\":131816,\"journal\":{\"name\":\"2015 Communication, Control and Intelligent Systems (CCIS)\",\"volume\":\"7 3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 Communication, Control and Intelligent Systems (CCIS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CCINTELS.2015.7437947\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 Communication, Control and Intelligent Systems (CCIS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CCINTELS.2015.7437947","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of UWB LNA using active resistors in 0.18µm CMOS technology
The proposed design of LNA uses common gate topology as an amplifying section. Noise cancelling technique is used and special emphasis is laid on the use of active resistors so that overall Noise figure is minimized and gain is enhanced. Simulation is done on ADS tool using 0.18μm technology. Power supply provided is 1.8V. Maximum gain achieved is 14.774dB. Noise figure achieved is 1dB to 1.6 dB over entire bandwidth. Bandwidth achieved is 3-9GHz.
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