沟槽外延和多外延哪个更冷?超沟槽功率MOS-FET (STM)突破硅极限的前沿方法

12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094) Pub Date : 2000-05-22 DOI:10.1109/ISPSD.2000.856776

T. Minato, T. Nitta, A. Uenisi, M. Yano, M. Harada, S. Hine

{"title":"沟槽外延和多外延哪个更冷?超沟槽功率MOS-FET (STM)突破硅极限的前沿方法","authors":"T. Minato, T. Nitta, A. Uenisi, M. Yano, M. Harada, S. Hine","doi":"10.1109/ISPSD.2000.856776","DOIUrl":null,"url":null,"abstract":"STM structure makes it possible to break through the Si limit via new RESURF effect in very tight periodic p and n columns repetition by using deep trench technology and trench sidewall ion implantation. In a wide breakdown voltage range from 200 to 1000 V, STM also gives greatly improved electrical characteristics at the cost of only one extra mask step in the DMOS fabrication wafer process procedure.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"43","resultStr":"{\"title\":\"Which is cooler, trench or multi-epitaxy? Cutting edge approach for the silicon limit by the super trench power MOS-FET (STM)\",\"authors\":\"T. Minato, T. Nitta, A. Uenisi, M. Yano, M. Harada, S. Hine\",\"doi\":\"10.1109/ISPSD.2000.856776\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"STM structure makes it possible to break through the Si limit via new RESURF effect in very tight periodic p and n columns repetition by using deep trench technology and trench sidewall ion implantation. In a wide breakdown voltage range from 200 to 1000 V, STM also gives greatly improved electrical characteristics at the cost of only one extra mask step in the DMOS fabrication wafer process procedure.\",\"PeriodicalId\":260241,\"journal\":{\"name\":\"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-05-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"43\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPSD.2000.856776\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.2000.856776","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 43

摘要

STM结构利用深沟槽技术和沟槽侧壁离子注入，使得在非常紧密的周期性p、n柱重复中利用新的RESURF效应突破Si极限成为可能。在从200到1000 V的宽击穿电压范围内，STM还以仅在DMOS制造晶圆工艺过程中增加一个掩膜步骤为代价，大大改善了电气特性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

Which is cooler, trench or multi-epitaxy? Cutting edge approach for the silicon limit by the super trench power MOS-FET (STM)

STM structure makes it possible to break through the Si limit via new RESURF effect in very tight periodic p and n columns repetition by using deep trench technology and trench sidewall ion implantation. In a wide breakdown voltage range from 200 to 1000 V, STM also gives greatly improved electrical characteristics at the cost of only one extra mask step in the DMOS fabrication wafer process procedure.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)

自引率

0.00%

发文量

期刊最新文献

Complementary LDMOS transistors for a CMOS/BiCMOS process Using "Adaptive resurf" to improve the SOA of LDMOS transistors Evaluation of 600 V/100 A NPT-IGBT with a non-self-align shallow p-well formation techniques A novel free wheeling diode for 1700 V IGBT module Low voltage CMOS compatible power MOSFET for on-chip DC/DC converters