电磁兼容抗扰度仿真自动验证

2013 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo) Pub Date : 2013-12-01 DOI:10.1109/EMCCOMPO.2013.6735201

B. Vrignon, P. Caunegre, J. Shepherd, Jianfei Wu

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引用次数: 5

摘要

模拟电路模块的抗扰度已成为设计中的一大风险。本文提出了一种在设计阶段自动模拟电路磁化率的方法。更具体地说，我们提出了一种CAD工具，用于确定直接功率注入(DPI)下信号的失败/通过标准。该贡献描述了由LDO调节器验证的工具的功能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Automatic verification of EMC immunity by simulation

Immunity of analog circuit blocks is becoming a major design risk. This paper presents an automated methodology to simulate the susceptibility of a circuit during the design phase. More specifically, we propose a CAD tool which determines the fail/pass criteria of a signal under direct power injection (DPI). This contribution describes the function of the tool which is validated by a LDO regulator.

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2013 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo)

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