A timing library construction method aimed at improving routing efficiency for modern FPGAs

As Moore’s law indicates, the number of transistors on a chip doubles every 18 months, which guarantees many resourcedemanding applications can be implemented on these advanced chips. In order to fulfill this purpose, CAD tools should be precise and efficient. In this paper, we dig into FPGAs, which unavoidably require CAD tools to be configured. A new timing database construction method mainly focusing on reformatting the timing models of programmable interconnections and routing wires is proposed to improve routing efficiency for FPGAs. A contrast experiment has been carried out to compare routing efficiency with original and new database. The results of our experiment show that routing with this new database can implement circuits of high quality (1.000× critical path delay) within less time (0.994× original routing time). And it can at most route resource-demanding circuits within 0.787× original routing time.