K. Hu, Houbing Lu, Xu Wang, Feng Li, Xinxin Wang, Tianru Geng, Hang Yang, L. Han, G. Jin
{"title":"ATLAS小条状薄间隙腔i阶段触发升级的DAQ原型","authors":"K. Hu, Houbing Lu, Xu Wang, Feng Li, Xinxin Wang, Tianru Geng, Hang Yang, L. Han, G. Jin","doi":"10.1109/RTC.2016.7543072","DOIUrl":null,"url":null,"abstract":"We will present a DAQ prototype designed for the ATLAS small-strip Thin Gap Chamber (sTGC) Phase-I trigger upgrade. The prototype includes two VMM2 chips developed to read out the signals of the sTGC, a Xilinx Kintex-7 FPGA used for the VMM2 configuration and the events storage, and a Gigabit Ethernet Transceiver (GET) working at the physical layer. The features of the DAQ prototype are described in detail.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A DAQ prototype for the ATLAS small-strip Thin Gap Chamber Phase-I trigger upgrade\",\"authors\":\"K. Hu, Houbing Lu, Xu Wang, Feng Li, Xinxin Wang, Tianru Geng, Hang Yang, L. Han, G. Jin\",\"doi\":\"10.1109/RTC.2016.7543072\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We will present a DAQ prototype designed for the ATLAS small-strip Thin Gap Chamber (sTGC) Phase-I trigger upgrade. The prototype includes two VMM2 chips developed to read out the signals of the sTGC, a Xilinx Kintex-7 FPGA used for the VMM2 configuration and the events storage, and a Gigabit Ethernet Transceiver (GET) working at the physical layer. The features of the DAQ prototype are described in detail.\",\"PeriodicalId\":383702,\"journal\":{\"name\":\"2016 IEEE-NPSS Real Time Conference (RT)\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE-NPSS Real Time Conference (RT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RTC.2016.7543072\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE-NPSS Real Time Conference (RT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RTC.2016.7543072","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A DAQ prototype for the ATLAS small-strip Thin Gap Chamber Phase-I trigger upgrade
We will present a DAQ prototype designed for the ATLAS small-strip Thin Gap Chamber (sTGC) Phase-I trigger upgrade. The prototype includes two VMM2 chips developed to read out the signals of the sTGC, a Xilinx Kintex-7 FPGA used for the VMM2 configuration and the events storage, and a Gigabit Ethernet Transceiver (GET) working at the physical layer. The features of the DAQ prototype are described in detail.