采用碳纳米管场效应晶体管的超低功耗全加法器电路

K. Kumar, Chittineni Sahithi, R. Sahoo, S. K. Sahoo
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引用次数: 4

摘要

在MOSFET发明之后,器件的连续缩放就像摩尔在1970年所预测的那样。这种器件尺寸的减小在提高速度方面提供了更高的性能,在更高的芯片密度下以更低的成本降低功耗。同时,在纳米尺度下,通道长度不断减小,导致了短通道效应(SCE)。为了克服这些限制,提出了许多替代装置。在这些替代器件中,碳纳米管场效应晶体管(CNTFET)被认为是最有希望替代MOSFET的器件之一。CNTFET是一种场效应晶体管,其沟道区域使用碳纳米管(CNT)。本文利用cntfet设计了一个10晶体管加法器电路,并以此计算了功率、延迟和功率延迟积。然后我们计算了CMOS逻辑的所有这些性能参数,并将结果与CNTFET逻辑的结果进行了比较。对比显示,使用CNTFET的电路比其CMOS对应物消耗近80%的功率,因此优于CMOS设计。
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Ultra low power full adder circuit using carbon nanotube field effect transistor
After the invention of the MOSFET, continuous scaling of the device is going on as predicted by Moore in 1970. This reduction in device size is giving higher performance in terms of increased speed, lower power consumption at lower cost with greater chip density. At the same time, because of the scaling, the channel length is decreasing continuously leading to short-channel effects (SCE) in nanoscale regime. To overcome these limitations many alternate devices are proposed. Among these various alternative devices, carbon nanotube field effect transistor (CNTFET) is found to be one of the most promising alternatives for MOSFET. The CNTFET is a field effect transistor in which a carbon nanotube (CNT) is used in the channel region. In this paper we have used CNTFETs for designing a 10 transistor adder circuit, from which power, delay and power delay products are calculated. We have then calculated all these performance parameters for CMOS logic and compared the results with that obtained for CNTFET logic. The comparison shows circuits using CNTFET consumes almost 80 percent less power compared to its CMOS counterpart and hence advantageous over CMOS design.
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