K. Kumar, Chittineni Sahithi, R. Sahoo, S. K. Sahoo
{"title":"采用碳纳米管场效应晶体管的超低功耗全加法器电路","authors":"K. Kumar, Chittineni Sahithi, R. Sahoo, S. K. Sahoo","doi":"10.1109/ICPCES.2014.7062796","DOIUrl":null,"url":null,"abstract":"After the invention of the MOSFET, continuous scaling of the device is going on as predicted by Moore in 1970. This reduction in device size is giving higher performance in terms of increased speed, lower power consumption at lower cost with greater chip density. At the same time, because of the scaling, the channel length is decreasing continuously leading to short-channel effects (SCE) in nanoscale regime. To overcome these limitations many alternate devices are proposed. Among these various alternative devices, carbon nanotube field effect transistor (CNTFET) is found to be one of the most promising alternatives for MOSFET. The CNTFET is a field effect transistor in which a carbon nanotube (CNT) is used in the channel region. In this paper we have used CNTFETs for designing a 10 transistor adder circuit, from which power, delay and power delay products are calculated. We have then calculated all these performance parameters for CMOS logic and compared the results with that obtained for CNTFET logic. The comparison shows circuits using CNTFET consumes almost 80 percent less power compared to its CMOS counterpart and hence advantageous over CMOS design.","PeriodicalId":337074,"journal":{"name":"2014 International Conference on Power, Control and Embedded Systems (ICPCES)","volume":"46 3","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Ultra low power full adder circuit using carbon nanotube field effect transistor\",\"authors\":\"K. Kumar, Chittineni Sahithi, R. Sahoo, S. K. Sahoo\",\"doi\":\"10.1109/ICPCES.2014.7062796\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"After the invention of the MOSFET, continuous scaling of the device is going on as predicted by Moore in 1970. This reduction in device size is giving higher performance in terms of increased speed, lower power consumption at lower cost with greater chip density. At the same time, because of the scaling, the channel length is decreasing continuously leading to short-channel effects (SCE) in nanoscale regime. To overcome these limitations many alternate devices are proposed. Among these various alternative devices, carbon nanotube field effect transistor (CNTFET) is found to be one of the most promising alternatives for MOSFET. The CNTFET is a field effect transistor in which a carbon nanotube (CNT) is used in the channel region. In this paper we have used CNTFETs for designing a 10 transistor adder circuit, from which power, delay and power delay products are calculated. We have then calculated all these performance parameters for CMOS logic and compared the results with that obtained for CNTFET logic. The comparison shows circuits using CNTFET consumes almost 80 percent less power compared to its CMOS counterpart and hence advantageous over CMOS design.\",\"PeriodicalId\":337074,\"journal\":{\"name\":\"2014 International Conference on Power, Control and Embedded Systems (ICPCES)\",\"volume\":\"46 3\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 International Conference on Power, Control and Embedded Systems (ICPCES)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICPCES.2014.7062796\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 International Conference on Power, Control and Embedded Systems (ICPCES)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICPCES.2014.7062796","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Ultra low power full adder circuit using carbon nanotube field effect transistor
After the invention of the MOSFET, continuous scaling of the device is going on as predicted by Moore in 1970. This reduction in device size is giving higher performance in terms of increased speed, lower power consumption at lower cost with greater chip density. At the same time, because of the scaling, the channel length is decreasing continuously leading to short-channel effects (SCE) in nanoscale regime. To overcome these limitations many alternate devices are proposed. Among these various alternative devices, carbon nanotube field effect transistor (CNTFET) is found to be one of the most promising alternatives for MOSFET. The CNTFET is a field effect transistor in which a carbon nanotube (CNT) is used in the channel region. In this paper we have used CNTFETs for designing a 10 transistor adder circuit, from which power, delay and power delay products are calculated. We have then calculated all these performance parameters for CMOS logic and compared the results with that obtained for CNTFET logic. The comparison shows circuits using CNTFET consumes almost 80 percent less power compared to its CMOS counterpart and hence advantageous over CMOS design.