S. Ha, Chul Kim, Jongkil Park, Siddharth Joshi, G. Cauwenberghs
{"title":"能量回收集成了6.78 mbps数据,6.3 mw电力遥测,通过单个13.56 mhz感应链路","authors":"S. Ha, Chul Kim, Jongkil Park, Siddharth Joshi, G. Cauwenberghs","doi":"10.1109/VLSIC.2014.6858381","DOIUrl":null,"url":null,"abstract":"We present a power/data telemetry IC with a new data modulation scheme and simultaneous power transfer through a single inductive link. Data-driven synchronized single-cycle shorting of the secondary LC tank conserves reactive power while inducing an instantaneous voltage change at the primary side. Cyclic on-off keying time-encoded symbol mapping of the shorting cycle allows transmission of two data bits per four carrier cycles with simultaneous power transfer during non-shorting cycles. All timing control signals for rectification and data transmission are generated from a low-power clock recovery comparator and 22-phase 2× PLL. The 1-mm2 65-nm CMOS IC delivers up to 6.3-mW power and transmits 6.78-Mbps data with a BER of less than 5.9×10-7 over a single 1-cm 13.56-MHz inductive link.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":"{\"title\":\"Energy-recycling integrated 6.78-Mbps data 6.3-mW power telemetry over a single 13.56-MHz inductive link\",\"authors\":\"S. Ha, Chul Kim, Jongkil Park, Siddharth Joshi, G. Cauwenberghs\",\"doi\":\"10.1109/VLSIC.2014.6858381\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a power/data telemetry IC with a new data modulation scheme and simultaneous power transfer through a single inductive link. Data-driven synchronized single-cycle shorting of the secondary LC tank conserves reactive power while inducing an instantaneous voltage change at the primary side. Cyclic on-off keying time-encoded symbol mapping of the shorting cycle allows transmission of two data bits per four carrier cycles with simultaneous power transfer during non-shorting cycles. All timing control signals for rectification and data transmission are generated from a low-power clock recovery comparator and 22-phase 2× PLL. The 1-mm2 65-nm CMOS IC delivers up to 6.3-mW power and transmits 6.78-Mbps data with a BER of less than 5.9×10-7 over a single 1-cm 13.56-MHz inductive link.\",\"PeriodicalId\":381216,\"journal\":{\"name\":\"2014 Symposium on VLSI Circuits Digest of Technical Papers\",\"volume\":\"12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-06-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"13\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 Symposium on VLSI Circuits Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2014.6858381\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 Symposium on VLSI Circuits Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2014.6858381","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 13
摘要
我们提出了一种功率/数据遥测IC,具有新的数据调制方案,并通过单个感应链路同时传输功率。数据驱动的二次LC槽同步单周期短路在引起一次侧瞬时电压变化的同时节省了无功功率。短周期的循环开关键控时间编码符号映射允许每四个载波周期传输两个数据位,同时在非短周期期间传输功率。整流和数据传输的所有定时控制信号由低功耗时钟恢复比较器和22相2x锁相环产生。1 mm2 65nm CMOS IC提供高达6.3 mw的功率,传输6.78 mbps的数据,在单个1 cm 13.56 mhz电感链路上的误码小于5.9×10-7。
Energy-recycling integrated 6.78-Mbps data 6.3-mW power telemetry over a single 13.56-MHz inductive link
We present a power/data telemetry IC with a new data modulation scheme and simultaneous power transfer through a single inductive link. Data-driven synchronized single-cycle shorting of the secondary LC tank conserves reactive power while inducing an instantaneous voltage change at the primary side. Cyclic on-off keying time-encoded symbol mapping of the shorting cycle allows transmission of two data bits per four carrier cycles with simultaneous power transfer during non-shorting cycles. All timing control signals for rectification and data transmission are generated from a low-power clock recovery comparator and 22-phase 2× PLL. The 1-mm2 65-nm CMOS IC delivers up to 6.3-mW power and transmits 6.78-Mbps data with a BER of less than 5.9×10-7 over a single 1-cm 13.56-MHz inductive link.