{"title":"电子方案诊断中检验假设序列表示的形式化","authors":"A. Verlan, S. Polozhaenko","doi":"10.1109/ELNANO.2018.8477496","DOIUrl":null,"url":null,"abstract":"A procedure for formalized presentation of a sequence of test (verify) hypotheses in the course of checking the health of electronic devices when they are decomposed into subschema is developed. The procedure is brought to a practical algorithm that provides an effective (from the point of view of minimizing labor input) search for faulty subschemas of the electronic device.","PeriodicalId":269665,"journal":{"name":"2018 IEEE 38th International Conference on Electronics and Nanotechnology (ELNANO)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Formalization of Representation of Sequence of Test Hypotheses in Diagnosing Electronic Schemes\",\"authors\":\"A. Verlan, S. Polozhaenko\",\"doi\":\"10.1109/ELNANO.2018.8477496\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A procedure for formalized presentation of a sequence of test (verify) hypotheses in the course of checking the health of electronic devices when they are decomposed into subschema is developed. The procedure is brought to a practical algorithm that provides an effective (from the point of view of minimizing labor input) search for faulty subschemas of the electronic device.\",\"PeriodicalId\":269665,\"journal\":{\"name\":\"2018 IEEE 38th International Conference on Electronics and Nanotechnology (ELNANO)\",\"volume\":\"37 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE 38th International Conference on Electronics and Nanotechnology (ELNANO)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ELNANO.2018.8477496\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE 38th International Conference on Electronics and Nanotechnology (ELNANO)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ELNANO.2018.8477496","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Formalization of Representation of Sequence of Test Hypotheses in Diagnosing Electronic Schemes
A procedure for formalized presentation of a sequence of test (verify) hypotheses in the course of checking the health of electronic devices when they are decomposed into subschema is developed. The procedure is brought to a practical algorithm that provides an effective (from the point of view of minimizing labor input) search for faulty subschemas of the electronic device.
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