On-chip measurement of data jitter with sub-picosecond accuracy for 10Gb/s multilane CDRs

On-chip jitter measurement is demonstrated in a 10Gb/s CDR by correlating the phase detector outputs of two adjacent CDR lanes. The RMS jitter of the received data and an estimate of the jitter's power spectral density are then extracted without using an external reference clock. Circuits implemented in 65nm CMOS measure random jitter ranging from 0.85ps to 1.89ps in PRBS31 data with no more than 100fs error compared to an 80GS/s real-time oscilloscope. Sinusoidal jitter of 0.89ps to 5.1ps is measured with a worst-case error of 580fS compared to the oscilloscope.