从晶体管到栅极的CMOS技术的自动逻辑提取器

25th ACM/IEEE, Design Automation Conference.Proceedings 1988. Pub Date : 1988-06-01 DOI:10.1109/DAC.1988.14809

M. Boehner

{"title":"从晶体管到栅极的CMOS技术的自动逻辑提取器","authors":"M. Boehner","doi":"10.1109/DAC.1988.14809","DOIUrl":null,"url":null,"abstract":"A program for automatic extraction of a gate-level description from a transistor-level description based on the layout of a CMOS VLSI circuit is presented. The extraction algorithm combines transistors to gates to arbitrary complexity without the help of any cell library. The resulting gate-level description provides the input for a digital logic simulator for further investigations.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"52 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"42","resultStr":"{\"title\":\"LOGEX-an automatic logic extractor from transistor to gate level for CMOS technology\",\"authors\":\"M. Boehner\",\"doi\":\"10.1109/DAC.1988.14809\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A program for automatic extraction of a gate-level description from a transistor-level description based on the layout of a CMOS VLSI circuit is presented. The extraction algorithm combines transistors to gates to arbitrary complexity without the help of any cell library. The resulting gate-level description provides the input for a digital logic simulator for further investigations.<<ETX>>\",\"PeriodicalId\":230716,\"journal\":{\"name\":\"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.\",\"volume\":\"52 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"42\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DAC.1988.14809\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DAC.1988.14809","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 42

摘要

提出了一种基于CMOS VLSI电路布局的从晶体管级描述中自动提取门级描述的程序。该提取算法将晶体管和门结合在一起，不需要任何单元库的帮助。由此产生的门级描述为数字逻辑模拟器的进一步研究提供了输入。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

LOGEX-an automatic logic extractor from transistor to gate level for CMOS technology

A program for automatic extraction of a gate-level description from a transistor-level description based on the layout of a CMOS VLSI circuit is presented. The extraction algorithm combines transistors to gates to arbitrary complexity without the help of any cell library. The resulting gate-level description provides the input for a digital logic simulator for further investigations.<>

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

25th ACM/IEEE, Design Automation Conference.Proceedings 1988.

自引率

0.00%

发文量

期刊最新文献

Automatic building of graphs for rectangular dualisation (IC floorplanning) Parameterized schematics (VLSI) Experience with the VHDL environment LocusRoute: a parallel global router for standard cells How to obtain more compactable channel routing solutions