I-Cheng Lin, Chuan-Jane Chao, M. Ker, J. Tseng, Chung-Ti Hsu, L. Leu, Yu-Lin Chen, Chia-Ku Tsai, Ren-Wen Huang
{"title":"高压CMOS IC产品中ESD保护二极管的闭锁测试诱发故障","authors":"I-Cheng Lin, Chuan-Jane Chao, M. Ker, J. Tseng, Chung-Ti Hsu, L. Leu, Yu-Lin Chen, Chia-Ku Tsai, Ren-Wen Huang","doi":"10.1109/EOSESD.2004.5272617","DOIUrl":null,"url":null,"abstract":"An EOS-like latchup failure occurred in a high-voltage IC product during latchup test and was identified within ESD diodes themselves. A parasitic npn bipolar formed by ESD protection diodes was trigger-activated and produced large current to result in EOS failure. This was verified by electrical measurement from TLP and curve-tracer as well as physical failure analysis. Corresponding layout solutions were proposed and solved this anomalous latchup failure successfully. Therefore ESD protection diode should be laid carefully for true latchup-robust design.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"43 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Latchup test-induced failure within ESD protection diodes in a high-voltage CMOS IC product\",\"authors\":\"I-Cheng Lin, Chuan-Jane Chao, M. Ker, J. Tseng, Chung-Ti Hsu, L. Leu, Yu-Lin Chen, Chia-Ku Tsai, Ren-Wen Huang\",\"doi\":\"10.1109/EOSESD.2004.5272617\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An EOS-like latchup failure occurred in a high-voltage IC product during latchup test and was identified within ESD diodes themselves. A parasitic npn bipolar formed by ESD protection diodes was trigger-activated and produced large current to result in EOS failure. This was verified by electrical measurement from TLP and curve-tracer as well as physical failure analysis. Corresponding layout solutions were proposed and solved this anomalous latchup failure successfully. Therefore ESD protection diode should be laid carefully for true latchup-robust design.\",\"PeriodicalId\":302866,\"journal\":{\"name\":\"2004 Electrical Overstress/Electrostatic Discharge Symposium\",\"volume\":\"43 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 Electrical Overstress/Electrostatic Discharge Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EOSESD.2004.5272617\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 Electrical Overstress/Electrostatic Discharge Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EOSESD.2004.5272617","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Latchup test-induced failure within ESD protection diodes in a high-voltage CMOS IC product
An EOS-like latchup failure occurred in a high-voltage IC product during latchup test and was identified within ESD diodes themselves. A parasitic npn bipolar formed by ESD protection diodes was trigger-activated and produced large current to result in EOS failure. This was verified by electrical measurement from TLP and curve-tracer as well as physical failure analysis. Corresponding layout solutions were proposed and solved this anomalous latchup failure successfully. Therefore ESD protection diode should be laid carefully for true latchup-robust design.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
