Large-scale MIMO detection design and FPGA implementations using SOR method

In this paper, we propose a very large scale integration design method for a large-scale multiple-input multiple-output detection algorithm. Our design uses a modified version of the Successive Over Relaxation (SOR) method, which substantially reduces the highly computational complexity of data detection and achieves the near-optimal performance. We use a reconfigurable Processing Elements Array (PEA) to compute matrix-vector or matrix-matrix in SOR Method, which reduces the complexity of linear data detection. Then we implement our design on Xilinx Virtex-7 FPGA and the experimental results show that SOR method has a superior performance over conventional methods.