Yuan Yao, Xuefeng Yu, Dayu Yang, F. Dai, J. Irwin, R. Jaeger
{"title":"采用SiGe技术的3位20GS/s交错闪存模数转换器","authors":"Yuan Yao, Xuefeng Yu, Dayu Yang, F. Dai, J. Irwin, R. Jaeger","doi":"10.1109/ASSCC.2007.4425720","DOIUrl":null,"url":null,"abstract":"A 3-bit analog-to-digital converter (ADC) for software defined radio applications that can work at a sampling rate of 20 GS/s is presented in this paper. In order to operate at Ku-band, two flash current mode logic (CML) ADCs are time-interleaved to achieve a 20 GHz sampling rate. A 3-bit current-steering digital-to-analog converter (DAC) is also designed for testing the high-speed ADC. The ADC-DAC RFIC is implemented in a 0.12 mum SiGe technology and occupies an area of 1.5 times 1.7 mm2. The total power consumption for the entire ADC-DAC chip is 2.36 W with a 4.2 V power supply. The ADC-DAC RFIC is packaged in a 44-pin CLLC package and achieves a peak spurious free dynamic range (SFDR) of 30.5 dBc and a peak effective number of bits (ENOB) of 2.8 bits at a 20 GS/s sampling rate.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"A 3-bit 20GS/s interleaved flash analog-to-digital converter in SiGe technology\",\"authors\":\"Yuan Yao, Xuefeng Yu, Dayu Yang, F. Dai, J. Irwin, R. Jaeger\",\"doi\":\"10.1109/ASSCC.2007.4425720\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 3-bit analog-to-digital converter (ADC) for software defined radio applications that can work at a sampling rate of 20 GS/s is presented in this paper. In order to operate at Ku-band, two flash current mode logic (CML) ADCs are time-interleaved to achieve a 20 GHz sampling rate. A 3-bit current-steering digital-to-analog converter (DAC) is also designed for testing the high-speed ADC. The ADC-DAC RFIC is implemented in a 0.12 mum SiGe technology and occupies an area of 1.5 times 1.7 mm2. The total power consumption for the entire ADC-DAC chip is 2.36 W with a 4.2 V power supply. The ADC-DAC RFIC is packaged in a 44-pin CLLC package and achieves a peak spurious free dynamic range (SFDR) of 30.5 dBc and a peak effective number of bits (ENOB) of 2.8 bits at a 20 GS/s sampling rate.\",\"PeriodicalId\":186095,\"journal\":{\"name\":\"2007 IEEE Asian Solid-State Circuits Conference\",\"volume\":\"21 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Asian Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2007.4425720\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2007.4425720","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 3-bit 20GS/s interleaved flash analog-to-digital converter in SiGe technology
A 3-bit analog-to-digital converter (ADC) for software defined radio applications that can work at a sampling rate of 20 GS/s is presented in this paper. In order to operate at Ku-band, two flash current mode logic (CML) ADCs are time-interleaved to achieve a 20 GHz sampling rate. A 3-bit current-steering digital-to-analog converter (DAC) is also designed for testing the high-speed ADC. The ADC-DAC RFIC is implemented in a 0.12 mum SiGe technology and occupies an area of 1.5 times 1.7 mm2. The total power consumption for the entire ADC-DAC chip is 2.36 W with a 4.2 V power supply. The ADC-DAC RFIC is packaged in a 44-pin CLLC package and achieves a peak spurious free dynamic range (SFDR) of 30.5 dBc and a peak effective number of bits (ENOB) of 2.8 bits at a 20 GS/s sampling rate.
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