A. Moscatelli, A. Merlini, G. Croce, P. Galbiati, C. Contiero
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LDMOS implementation in a 0.35 /spl mu/m BCD technology (BCD6)
This paper presents the integration approach followed to implement power LDMOS' up to 60 V into a 0.35 /spl mu/m process technology (BCD6) based on a CMOS plus Flash-Memory platform of equivalent lithography generation, built on a P-over P+ substrate. Experimental results on LDMOS' in terms of on-state specific resistance, off and on-state breakdown voltage, frequency behavior will be described analyzing the interactions between low voltage ULSI platform and high voltage power elements.
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