用于小规模集成的逻辑CMOS兼容闪存EEPROM

Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442) Pub Date : 1900-01-01 DOI:10.1109/ICM.2003.237930

M. Shalchian, S. M. Atarodi

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引用次数: 4

摘要

提出了一种单聚浮栅非易失性存储单元。在该器件中，为了使器件与标准逻辑CMOS工艺兼容，将第二多晶硅层去除。采用标准的0.25 /spl μ m CMOS工艺，采用特殊的结构，制备了具有高存储密度的电池阵列。所有的记忆单元都能承受60000次的耐久性测试，并能保持10年的数据。使用该单元，一个小到中等尺寸(通常为64k *8b)的闪存EEPROM阵列将集成在标准逻辑CMOS工艺中。

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A logic CMOS compatible Flash EEPROM for small scale integration

A single-poly floating gate non volatile memory cell is presented. In this device the second poly layer is removed to make the device compatible with standard logic CMOS process. An array of cells with high storage density has been fabricated on a standard 0.25 /spl mu/m CMOS process with a special architecture. All memory cells tolerate 60000 cycles of endurance test and show 10 years of data retention. Using this cell, a small to medium size (typically 64 K*8b) Flash EEPROM array would be integrated in standard logic CMOS process.

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Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)

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