A Fully-Dynamic Time-Interleaved Noise-Shaping SAR ADC Based on CIFF Architecture

This paper presents a fully-dynamic, low-power, and wide-band time-interleaved (TI) noise-shaping (NS) SAR ADC based on the cascade of integrators with feed-forward (CIFF) architecture. Its loop filter and interleaving operation are realized by fully-passive switched capacitor (SC) circuits. Its feedforward summation is implemented by using a multi-path comparator. Moreover, its overall noise transfer function (NTF) is set by device ratios and highly robust against process, voltage, and temperature (PVT) variations. It allows the loop filter poles to be placed close to the unit circle. Comparing to a recently published TI NS SAR ADC based on the error-feedback (EF) structure, this work obviates the need for amplifiers with static current, saving power. It also eliminates the dependence of NTF on the amplifier gain, which is PVT sensitive. A prototype ADC in 40nm process achieves 69.1dB SNDR over 50MHz BW while consuming only 8.5mW from a 1.1V supply, leading to a Walden FoM of 36.3fJ/conv.-step.