{"title":"集成守护模块在收缩体系结构内部处理单元寻址中的应用","authors":"B. B. Petrov","doi":"10.1109/ET50336.2020.9238281","DOIUrl":null,"url":null,"abstract":"FPGA programmable logic devices make it possible to implement known and synthesize new architectures with many applications. Increasingly, these implementations are based on systolic array that combine very good capabilities and features. The article discusses a method for shortening additional resource for change of a specific parametric value in a given computing element of the systolic architecture by embedding a small single-register module in each cell.","PeriodicalId":178356,"journal":{"name":"2020 XXIX International Scientific Conference Electronics (ET)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Using of Integrated Daemon Module for Internal Processing Cells Addressing in Systolic Architecture\",\"authors\":\"B. B. Petrov\",\"doi\":\"10.1109/ET50336.2020.9238281\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"FPGA programmable logic devices make it possible to implement known and synthesize new architectures with many applications. Increasingly, these implementations are based on systolic array that combine very good capabilities and features. The article discusses a method for shortening additional resource for change of a specific parametric value in a given computing element of the systolic architecture by embedding a small single-register module in each cell.\",\"PeriodicalId\":178356,\"journal\":{\"name\":\"2020 XXIX International Scientific Conference Electronics (ET)\",\"volume\":\"79 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-09-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 XXIX International Scientific Conference Electronics (ET)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ET50336.2020.9238281\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 XXIX International Scientific Conference Electronics (ET)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ET50336.2020.9238281","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Using of Integrated Daemon Module for Internal Processing Cells Addressing in Systolic Architecture
FPGA programmable logic devices make it possible to implement known and synthesize new architectures with many applications. Increasingly, these implementations are based on systolic array that combine very good capabilities and features. The article discusses a method for shortening additional resource for change of a specific parametric value in a given computing element of the systolic architecture by embedding a small single-register module in each cell.