{"title":"简化IEEE 1284软IP设计,实现系统集成电路","authors":"Jung-Han Lee, Dong-Wook Kim, W. Cho","doi":"10.1109/APASIC.1999.824081","DOIUrl":null,"url":null,"abstract":"The authors propose an IEEE 1284 soft IP for system IC implementation. They designed a reduced mode for high-speed and small gate count. The designed IP can be used as a system IC. After simulation the authors verified the designed IP for specific process technology for an actual system IC design process. Finally, they considered which form of IP can be used efficiently for the algorithm level of system IC design.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Reduced IEEE 1284 soft IP design for system IC implementation\",\"authors\":\"Jung-Han Lee, Dong-Wook Kim, W. Cho\",\"doi\":\"10.1109/APASIC.1999.824081\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors propose an IEEE 1284 soft IP for system IC implementation. They designed a reduced mode for high-speed and small gate count. The designed IP can be used as a system IC. After simulation the authors verified the designed IP for specific process technology for an actual system IC design process. Finally, they considered which form of IP can be used efficiently for the algorithm level of system IC design.\",\"PeriodicalId\":346808,\"journal\":{\"name\":\"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)\",\"volume\":\"49 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-08-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APASIC.1999.824081\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APASIC.1999.824081","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Reduced IEEE 1284 soft IP design for system IC implementation
The authors propose an IEEE 1284 soft IP for system IC implementation. They designed a reduced mode for high-speed and small gate count. The designed IP can be used as a system IC. After simulation the authors verified the designed IP for specific process technology for an actual system IC design process. Finally, they considered which form of IP can be used efficiently for the algorithm level of system IC design.