{"title":"使用安全操作区域来评估由于工艺变化而导致的逻辑电路的错误概率","authors":"U. Khalid, A. Mastrandrea, M. Olivieri","doi":"10.1109/IIRW.2013.6804188","DOIUrl":null,"url":null,"abstract":"Process variations in conjunction to voltage noise can be responsible of logic errors in digital circuits. The variations in process-induced parameters affect the probability of noise-induced faulty operation of digital logic cells. This work introduces the concept of “safe operation region” to allow an efficient Monte Carlo evaluation of the associated error probability, avoiding time-consuming circuit level or device level Monte Carlo simulations.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Using safe operation regions to assess the error probability of logic circuits due to process variations\",\"authors\":\"U. Khalid, A. Mastrandrea, M. Olivieri\",\"doi\":\"10.1109/IIRW.2013.6804188\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Process variations in conjunction to voltage noise can be responsible of logic errors in digital circuits. The variations in process-induced parameters affect the probability of noise-induced faulty operation of digital logic cells. This work introduces the concept of “safe operation region” to allow an efficient Monte Carlo evaluation of the associated error probability, avoiding time-consuming circuit level or device level Monte Carlo simulations.\",\"PeriodicalId\":287904,\"journal\":{\"name\":\"2013 IEEE International Integrated Reliability Workshop Final Report\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE International Integrated Reliability Workshop Final Report\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IIRW.2013.6804188\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE International Integrated Reliability Workshop Final Report","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IIRW.2013.6804188","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Using safe operation regions to assess the error probability of logic circuits due to process variations
Process variations in conjunction to voltage noise can be responsible of logic errors in digital circuits. The variations in process-induced parameters affect the probability of noise-induced faulty operation of digital logic cells. This work introduces the concept of “safe operation region” to allow an efficient Monte Carlo evaluation of the associated error probability, avoiding time-consuming circuit level or device level Monte Carlo simulations.
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