Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804179
W. Zisser, H. Ceric, R. L. de Orio, S. Selberherr
A study of electromigration in open through silicon vias (TSVs) is presented. The calculations are based on the drift-diffusion model for electromigration combined with mechanical simulations. The results show that the highest stresses are located at the aluminium/tungsten interfaces, near the region where the electrical current is introduced into the TSV, which happens to be the location of the highest current density at the interface there, the electromigration induced degradation, e.g. void nucleation, is most probable to occur.
{"title":"Electromigration induced stress in open TSVs","authors":"W. Zisser, H. Ceric, R. L. de Orio, S. Selberherr","doi":"10.1109/IIRW.2013.6804179","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804179","url":null,"abstract":"A study of electromigration in open through silicon vias (TSVs) is presented. The calculations are based on the drift-diffusion model for electromigration combined with mechanical simulations. The results show that the highest stresses are located at the aluminium/tungsten interfaces, near the region where the electrical current is introduced into the TSV, which happens to be the location of the highest current density at the interface there, the electromigration induced degradation, e.g. void nucleation, is most probable to occur.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115286963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804169
S. C. Chen, C. L. Chen, Y. Lee, S. W. Chang, J. Shih, Y. Lee, D. Maji, K. Wu
In this paper, a reliable TDDB lifetime projection by modeling the gate leakage current degradation is proposed. The validity of model is demonstrated by the good agreements with the experimental results. The two-stage Ig degradation and voltage-dependent Weibull slope are explained through the associated trap generation during the TDDB stress. Based on this model., accurate TDDB lifetime prediction can be achieved for HK/IL gate stack.
{"title":"A reliable TDDB lifetime Projection model for advanced gate stack","authors":"S. C. Chen, C. L. Chen, Y. Lee, S. W. Chang, J. Shih, Y. Lee, D. Maji, K. Wu","doi":"10.1109/IIRW.2013.6804169","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804169","url":null,"abstract":"In this paper, a reliable TDDB lifetime projection by modeling the gate leakage current degradation is proposed. The validity of model is demonstrated by the good agreements with the experimental results. The two-stage Ig degradation and voltage-dependent Weibull slope are explained through the associated trap generation during the TDDB stress. Based on this model., accurate TDDB lifetime prediction can be achieved for HK/IL gate stack.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122561280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804190
K. Seidel, W. Weinreich, P. Polakowski, D. Triyoso, M. Nolan, K. Yiang, S. Chu
In this paper, the authors have shown that the Al-doping concentration of ZrO2 based dielectrics in BEOL has a big influence on electrical properties and reliability. Despite steep field acceleration behavior undoped ZrO2 suffers from early failures and uncontrolled leakage mechanisms. High Al-concentrations also show higher leakage current and less reliability. It is recommended to apply only small Al-doping concentrations in order to benefit from good field acceleration and capacitance density as well as low leakage current.
{"title":"Reliability comparison of pure ZrO2 and Al− doped ZrO2 MIM capacitors","authors":"K. Seidel, W. Weinreich, P. Polakowski, D. Triyoso, M. Nolan, K. Yiang, S. Chu","doi":"10.1109/IIRW.2013.6804190","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804190","url":null,"abstract":"In this paper, the authors have shown that the Al-doping concentration of ZrO2 based dielectrics in BEOL has a big influence on electrical properties and reliability. Despite steep field acceleration behavior undoped ZrO2 suffers from early failures and uncontrolled leakage mechanisms. High Al-concentrations also show higher leakage current and less reliability. It is recommended to apply only small Al-doping concentrations in order to benefit from good field acceleration and capacitance density as well as low leakage current.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121613038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804188
U. Khalid, A. Mastrandrea, M. Olivieri
Process variations in conjunction to voltage noise can be responsible of logic errors in digital circuits. The variations in process-induced parameters affect the probability of noise-induced faulty operation of digital logic cells. This work introduces the concept of “safe operation region” to allow an efficient Monte Carlo evaluation of the associated error probability, avoiding time-consuming circuit level or device level Monte Carlo simulations.
{"title":"Using safe operation regions to assess the error probability of logic circuits due to process variations","authors":"U. Khalid, A. Mastrandrea, M. Olivieri","doi":"10.1109/IIRW.2013.6804188","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804188","url":null,"abstract":"Process variations in conjunction to voltage noise can be responsible of logic errors in digital circuits. The variations in process-induced parameters affect the probability of noise-induced faulty operation of digital logic cells. This work introduces the concept of “safe operation region” to allow an efficient Monte Carlo evaluation of the associated error probability, avoiding time-consuming circuit level or device level Monte Carlo simulations.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133186592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804176
G. Wirth
We have performed statistical compact modeling of low-frequency (LF) noise in MOSFETs under large signal periodic (AC or cyclo-stationary) excitation, addressing relevant open issues in the literature. In the present work we introduce an equivalent Fermi level for cyclo-stationary excitation, unifying modeling of LF noise under constant (DC) bias and large signal periodic excitation. Results are compared to relevant experimental data from the literature, and Monte Carlo simulations are performed. The model is optimized for implementation into standard circuit simulators.
{"title":"Large signal statistical compact model for LF noise","authors":"G. Wirth","doi":"10.1109/IIRW.2013.6804176","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804176","url":null,"abstract":"We have performed statistical compact modeling of low-frequency (LF) noise in MOSFETs under large signal periodic (AC or cyclo-stationary) excitation, addressing relevant open issues in the literature. In the present work we introduce an equivalent Fermi level for cyclo-stationary excitation, unifying modeling of LF noise under constant (DC) bias and large signal periodic excitation. Results are compared to relevant experimental data from the literature, and Monte Carlo simulations are performed. The model is optimized for implementation into standard circuit simulators.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124364840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804171
C. Lee, S.K. Park, J.-K. Kim, S.-H Kim, S.J. Kwon, H.-W Kim, Yuchul Hwang, Y. Park
Recently long-channel PMOS transistors are being used in delay circuits to increase delay time. Negative Bias Temperature Instability (NBTI) has channel length dependency which shows that long-channel devices degrade more than short channel devices. We suggest a source underlap structure with short channel transistor to solve this problem. We confirmed the short-channel device with underlap structure shows improved NBTI characteristics compared to normal long-channel device through a device simulation.
{"title":"Improving the NBTI characteristics of long-channel PMOSFETs by short channel with source underlap structure","authors":"C. Lee, S.K. Park, J.-K. Kim, S.-H Kim, S.J. Kwon, H.-W Kim, Yuchul Hwang, Y. Park","doi":"10.1109/IIRW.2013.6804171","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804171","url":null,"abstract":"Recently long-channel PMOS transistors are being used in delay circuits to increase delay time. Negative Bias Temperature Instability (NBTI) has channel length dependency which shows that long-channel devices degrade more than short channel devices. We suggest a source underlap structure with short channel transistor to solve this problem. We confirmed the short-channel device with underlap structure shows improved NBTI characteristics compared to normal long-channel device through a device simulation.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128627705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804158
P. Shrestha, D. Nminibapiel, J. Campbell, K. Cheung, H. Baumgart, S. Deora, G. Bersuker
The characteristics of a conductive filament in HfO2 RRAM is shown to be dependent on the duration of the current compliance overshoot, which may occur during the filament formation process. In addition to the overshoot amplitude, the filament resistance is found to be affected by the duration of the overshoot caused by the parasitic capacitance.
{"title":"Dependence of the filament resistance on the duration of current overshoot","authors":"P. Shrestha, D. Nminibapiel, J. Campbell, K. Cheung, H. Baumgart, S. Deora, G. Bersuker","doi":"10.1109/IIRW.2013.6804158","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804158","url":null,"abstract":"The characteristics of a conductive filament in HfO2 RRAM is shown to be dependent on the duration of the current compliance overshoot, which may occur during the filament formation process. In addition to the overshoot amplitude, the filament resistance is found to be affected by the duration of the overshoot caused by the parasitic capacitance.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125526833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804186
Fengying Qiao, L. Pan, Xuemei Liu, Haozhi Ma, Dong Wu, Jun Xu
The total ionizing dose (TID) radiation response of a flash memory circuit including high voltage (HV) periphery was studied. We show that functional failure of the charge pumps (CP) is mostly caused by an increased load current, due to radiation induced leakage current in the HV pass transistors. This leads to a failure to program/erase the array in turn.
{"title":"Investigation of TID degradation of high voltage circuits in flash memory","authors":"Fengying Qiao, L. Pan, Xuemei Liu, Haozhi Ma, Dong Wu, Jun Xu","doi":"10.1109/IIRW.2013.6804186","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804186","url":null,"abstract":"The total ionizing dose (TID) radiation response of a flash memory circuit including high voltage (HV) periphery was studied. We show that functional failure of the charge pumps (CP) is mostly caused by an increased load current, due to radiation induced leakage current in the HV pass transistors. This leads to a failure to program/erase the array in turn.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123245961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804175
Xinhua Wang, Yuan-qi Jiang, Sen Huang, Yingkui Zheng, K. Wei, Xiaojuan Chen, W. Luo, Guoguo Liu, L. Pang, T. Yuan, Xinyu Liu
We have performed constant voltage stress (CVS) tests on GaN-on-SiC HEMT to investigate the drain current drift. Two kinds of current drift behavior are observed in CVS. The off-state drain voltage step stress tests are carried out to confirm the electric field dependent current drift. A critical voltage for drain current recovery is observed. We suggest that the recovery of drain current is due to holes generation near the heterojunction interface or the detrapping of acceptors in the barrier layer. The drain current drift is balanced by the current degradation and recovery mechanism.
{"title":"Electric field dependent drain current drift of AlGaN/GaN HEMT","authors":"Xinhua Wang, Yuan-qi Jiang, Sen Huang, Yingkui Zheng, K. Wei, Xiaojuan Chen, W. Luo, Guoguo Liu, L. Pang, T. Yuan, Xinyu Liu","doi":"10.1109/IIRW.2013.6804175","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804175","url":null,"abstract":"We have performed constant voltage stress (CVS) tests on GaN-on-SiC HEMT to investigate the drain current drift. Two kinds of current drift behavior are observed in CVS. The off-state drain voltage step stress tests are carried out to confirm the electric field dependent current drift. A critical voltage for drain current recovery is observed. We suggest that the recovery of drain current is due to holes generation near the heterojunction interface or the detrapping of acceptors in the barrier layer. The drain current drift is balanced by the current degradation and recovery mechanism.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"374 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116128725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804166
Z. Chbili, K. Cheung, P. Campbell, J. Suehle, D. Ioannou, S. Ryu, A. Lelis
We observe an unusual instability in the SiC DMOSFET transistor characteristics. From a series of bias conditions at elevated temperatures, we conclude that a high density of hole traps in the oxide near the SiO2/SiC interface are responsible.
{"title":"Unusual bias temperature instability in SiC DMOSFET","authors":"Z. Chbili, K. Cheung, P. Campbell, J. Suehle, D. Ioannou, S. Ryu, A. Lelis","doi":"10.1109/IIRW.2013.6804166","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804166","url":null,"abstract":"We observe an unusual instability in the SiC DMOSFET transistor characteristics. From a series of bias conditions at elevated temperatures, we conclude that a high density of hole traps in the oxide near the SiO2/SiC interface are responsible.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125445085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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