{"title":"结合自适应量化和基于qtd的片上压缩处理器的CMOS图像传感器","authors":"Shoushun Chen, A. Bermak, Wang Yan, D. Martinez","doi":"10.1109/CICC.2006.320903","DOIUrl":null,"url":null,"abstract":"In this paper, a CMOS image sensor with on-chip compression processor is proposed. An adaptive quantization scheme based on boundary adaptation procedure followed by an on-line quadrant tree decomposition processing is proposed enabling low power, robust and compact image compression processor. The image sensor chip has been implemented using 0.35 mu CMOS technology and operates at 3.3 V. Simulation and experimental results show compression figures corresponding to 0.6-0.8 BPP, while maintaining reasonable PSNR levels and very low operating power consumption","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A CMOS Image Sensor with combined adaptive-quantization and QTD-based on-chip compression processor\",\"authors\":\"Shoushun Chen, A. Bermak, Wang Yan, D. Martinez\",\"doi\":\"10.1109/CICC.2006.320903\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a CMOS image sensor with on-chip compression processor is proposed. An adaptive quantization scheme based on boundary adaptation procedure followed by an on-line quadrant tree decomposition processing is proposed enabling low power, robust and compact image compression processor. The image sensor chip has been implemented using 0.35 mu CMOS technology and operates at 3.3 V. Simulation and experimental results show compression figures corresponding to 0.6-0.8 BPP, while maintaining reasonable PSNR levels and very low operating power consumption\",\"PeriodicalId\":269854,\"journal\":{\"name\":\"IEEE Custom Integrated Circuits Conference 2006\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Custom Integrated Circuits Conference 2006\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2006.320903\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Custom Integrated Circuits Conference 2006","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2006.320903","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
摘要
本文提出了一种带有片上压缩处理器的CMOS图像传感器。提出了一种基于边界自适应过程和在线象限树分解处理的自适应量化方案，使图像压缩处理器具有低功耗、鲁棒性和紧凑性。该图像传感器芯片采用0.35 mu CMOS技术实现，工作电压为3.3 V。仿真和实验结果表明，在保持合理的PSNR水平和极低的运行功耗的情况下，压缩数字对应于0.6-0.8 BPP
A CMOS Image Sensor with combined adaptive-quantization and QTD-based on-chip compression processor
In this paper, a CMOS image sensor with on-chip compression processor is proposed. An adaptive quantization scheme based on boundary adaptation procedure followed by an on-line quadrant tree decomposition processing is proposed enabling low power, robust and compact image compression processor. The image sensor chip has been implemented using 0.35 mu CMOS technology and operates at 3.3 V. Simulation and experimental results show compression figures corresponding to 0.6-0.8 BPP, while maintaining reasonable PSNR levels and very low operating power consumption
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