{"title":"一种适用于低功耗、低失真数字D类放大器的脉宽调制采样方法","authors":"Huiyan Li, B. Gwee, J.S. Chang, M. T. Tan","doi":"10.1109/MWSCAS.2000.951696","DOIUrl":null,"url":null,"abstract":"A PWM sampling process for low-power digital Class D amplifiers with low harmonic distortion is proposed. By means of a novel algorithm, the Natural Sampling Process is emulated through a Delta-Compensation Uniform Sampling Process. This algorithm features a simple circuit implementation (small IC area), low power operation (low sampling rate) and a highly desirable low harmonic distortion.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A novel pulse width modulation sampling process for low power, low distortion digital Class D amplifiers\",\"authors\":\"Huiyan Li, B. Gwee, J.S. Chang, M. T. Tan\",\"doi\":\"10.1109/MWSCAS.2000.951696\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A PWM sampling process for low-power digital Class D amplifiers with low harmonic distortion is proposed. By means of a novel algorithm, the Natural Sampling Process is emulated through a Delta-Compensation Uniform Sampling Process. This algorithm features a simple circuit implementation (small IC area), low power operation (low sampling rate) and a highly desirable low harmonic distortion.\",\"PeriodicalId\":437349,\"journal\":{\"name\":\"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)\",\"volume\":\"37 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-08-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2000.951696\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2000.951696","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A novel pulse width modulation sampling process for low power, low distortion digital Class D amplifiers
A PWM sampling process for low-power digital Class D amplifiers with low harmonic distortion is proposed. By means of a novel algorithm, the Natural Sampling Process is emulated through a Delta-Compensation Uniform Sampling Process. This algorithm features a simple circuit implementation (small IC area), low power operation (low sampling rate) and a highly desirable low harmonic distortion.
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