R. Mathur, M. Kumar, V. Asthana, S. Aggarwal, S. Gupta, D. Wanjul, A. Baradia, S. Thota, P. Jain, B. Zheng, A. Cubeta, S. Thyagarajan, A. Chen, Y. Chong
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5GHz SRAM for High-Performance Compute Platform in 5nm CMOS
Advances in 7nm and 5nm silicon process nodes push high-performance compute (HPC) to a new era of technological capabilities and unprecedented performance levels. This paper showcases the development of SRAM macros for a flagship HPC platform core targeted towards the infrastructure market (figure 1). A test vehicle in the 5nm FinFET process demonstrates L1 SRAM macro frequency of 5GHz with sub-120ps access times and a high bit density of L2 SRAM macro of 33.20 Mbit/mm2.
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