RF-Power Induced Clock Jitter Degradation and Its Modeling in High-Speed I/O Interfaces

This paper investigates jitter degradation of highspeed I/O when RF power sources, such as smartphone, are in proximity to the I/O link. The jitter is increased by as high as ~200% when a 500-mW LTE antenna is 3 cm away from the transmission line at 831 MHz and may cause failure of the high-speed link. An analytic model is developed to capture the jitter behavior at various RF amplitudes and clock slew-rates. A good agreement among the model, simulation, and measurement is obtained at various frequencies and with a measured LTE signal. This study may help to predict the jitter degradation due to adjacent RF power and may be more critical to I/O interfaces with higher speed.