{"title":"太级计算和互连挑战- 3D堆叠考虑","authors":"J. Bautista","doi":"10.1109/HOTCHIPS.2008.7476514","DOIUrl":null,"url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation. Discusses tera-scale computing and interconnect challenges. Suggests that 3D stacking is an attractive solution for both a large last level cache and increasing bulk DRAM capacities.","PeriodicalId":134939,"journal":{"name":"2008 IEEE Hot Chips 20 Symposium (HCS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Tera-scale computing and interconnect challenges - 3D stacking considerations\",\"authors\":\"J. Bautista\",\"doi\":\"10.1109/HOTCHIPS.2008.7476514\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article consists of a collection of slides from the author's conference presentation. Discusses tera-scale computing and interconnect challenges. Suggests that 3D stacking is an attractive solution for both a large last level cache and increasing bulk DRAM capacities.\",\"PeriodicalId\":134939,\"journal\":{\"name\":\"2008 IEEE Hot Chips 20 Symposium (HCS)\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 IEEE Hot Chips 20 Symposium (HCS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HOTCHIPS.2008.7476514\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE Hot Chips 20 Symposium (HCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HOTCHIPS.2008.7476514","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Tera-scale computing and interconnect challenges - 3D stacking considerations
This article consists of a collection of slides from the author's conference presentation. Discusses tera-scale computing and interconnect challenges. Suggests that 3D stacking is an attractive solution for both a large last level cache and increasing bulk DRAM capacities.
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